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Searched
refs:getImm
(Results
76 - 100
of
203
) sorted by null
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/external/llvm/lib/Target/ARM/
ARMMCInstLower.cpp
80
MCOp = MCOperand::CreateImm(MO.
getImm
());
Thumb2SizeReduction.cpp
477
if (MI->getOperand(3).
getImm
())
484
OffsetImm = MI->getOperand(2).
getImm
();
539
unsigned Imm = MI->getOperand(2).
getImm
();
547
if (MI->getOperand(3).
getImm
() != ARMCC::AL)
602
if (MI->getOperand(2).
getImm
() == 0)
673
unsigned Imm = MI->getOperand(2).
getImm
();
775
if (((unsigned)MO.
getImm
()) > Limit)
[
all
...]
ARMExpandPseudoInsts.cpp
513
unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).
getImm
();
[
all
...]
/external/llvm/lib/Target/Hexagon/
HexagonMCInstLower.cpp
68
MCO = MCOperand::CreateImm(MO.
getImm
());
HexagonExpandPredSpillCode.cpp
92
int Offset = MI->getOperand(1).
getImm
();
139
int Offset = MI->getOperand(2).
getImm
();
HexagonFixupHwLoops.cpp
176
.addImm(MII->getOperand(1).
getImm
());
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCInst.cpp
112
int ImmValue = MO.
getImm
();
/external/llvm/lib/Target/MSP430/
MSP430AsmPrinter.cpp
75
O << MO.
getImm
();
MSP430MCInstLower.cpp
130
MCOp = MCOperand::CreateImm(MO.
getImm
());
/external/llvm/lib/Target/Mips/
Mips16RegisterInfo.cpp
132
Offset += MI.getOperand(OpNo + 1).
getImm
();
MipsISelDAGToDAG.h
117
//
getImm
- Return a target constant with the specified value.
118
inline SDValue
getImm
(const SDNode *Node, uint64_t Imm) {
MipsSERegisterInfo.cpp
150
Offset += MI.getOperand(OpNo + 1).
getImm
();
/external/llvm/lib/Target/XCore/
XCoreInstrInfo.cpp
55
return op.isImm() && op.
getImm
() == 0;
297
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].
getImm
());
306
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].
getImm
());
420
Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].
getImm
()));
XCoreMCInstLower.cpp
92
return MCOperand::CreateImm(MO.
getImm
() + offset);
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/
lp_bld_debug.cpp
376
jump = pc + operand.
getImm
();
382
jump = (uint64_t)operand.
getImm
();
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
SIMCCodeEmitter.cpp
146
return MO.
getImm
();
182
return LITERAL_REG | (MI.getOperand(OpNo).
getImm
() << 32);
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
SystemZMCCodeEmitter.cpp
123
return static_cast<uint64_t>(MO.
getImm
());
188
Expr = MCConstantExpr::Create(MO.
getImm
() + Offset, Ctx);
/external/mesa3d/src/gallium/auxiliary/gallivm/
lp_bld_debug.cpp
376
jump = pc + operand.
getImm
();
382
jump = (uint64_t)operand.
getImm
();
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
SIMCCodeEmitter.cpp
146
return MO.
getImm
();
182
return LITERAL_REG | (MI.getOperand(OpNo).
getImm
() << 32);
/external/llvm/lib/CodeGen/
MachineInstr.cpp
179
return
getImm
() == Other.
getImm
();
221
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.
getImm
());
325
OS <<
getImm
();
[
all
...]
/external/llvm/lib/Target/R600/
R600InstrInfo.cpp
318
OpTable[j][1])).
getImm
();
341
getOperandIdx(MI->getOpcode(), OpTable[j][1])).
getImm
();
347
getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).
getImm
();
568
IG[i]->getOperand(Op).
getImm
());
801
PredSet->getOperand(2).setImm(Cond[1].
getImm
());
817
PredSet->getOperand(2).setImm(Cond[1].
getImm
());
920
if (MI->getOperand(3).
getImm
() != 0 || MI->getOperand(4).
getImm
() != 0)
968
switch (MO.
getImm
()) {
[
all
...]
AMDGPUMCInstLower.cpp
72
MCOp = MCOperand::CreateImm(MO.
getImm
());
/external/llvm/lib/Target/Sparc/
DelaySlotFiller.cpp
356
StructSize = MO.
getImm
();
409
&& (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).
getImm
() != 0))
442
int64_t imm = SetHiMI->getOperand(1).
getImm
();
/external/llvm/include/llvm/CodeGen/
StackMaps.h
69
+ MI->getOperand(getMetaIdx(NArgPos)).
getImm
();
/external/llvm/include/llvm/MC/
MCInst.h
74
int64_t
getImm
() const {
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