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    Searched refs:getRegClass (Results 26 - 50 of 93) sorted by null

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  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 123 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
124 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
602 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
638 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
673 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
674 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
676 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
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PPCFastISel.cpp 441 (ResultReg ? MRI.getRegClass(ResultReg) :
558 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
573 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
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  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 42 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
57 return TRI->getRegClass(RegClass);
361 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
366 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
422 MF.getRegInfo().getRegClass(MO.getReg());
MachineRegisterInfo.cpp 55 const TargetRegisterClass *OldRC = getRegClass(Reg);
71 const TargetRegisterClass *OldRC = getRegClass(Reg);
TailDuplication.cpp 299 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
404 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
441 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
451 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg));
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UnreachableBlockElim.cpp 197 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
RegisterCoalescer.cpp 283 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
285 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
290 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
291 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
647 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
778 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
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InlineSpiller.cpp 745 MRI.getRegClass(SVI.SpillReg), &TRI);
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RegAllocGreedy.cpp 518 (Size / SlotIndex::InstrDist) > (2 * MRI->getRegClass(Reg)->getNumRegs());
717 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
718 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
817 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
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CriticalAntiDepBreaker.cpp 185 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
309 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
MachineCSE.cpp 141 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
151 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
553 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
RegAllocPBQP.cpp 209 const TargetRegisterClass *trc = mri->getRegClass(vreg);
523 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
MachineLICM.cpp 786 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
    [all...]
MachineSSAUpdater.cpp 59 VRC = MRI->getRegClass(VR);
RegAllocFast.cpp 288 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
516 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
626 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
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MachineInstr.cpp     [all...]
TwoAddressInstructionPass.cpp     [all...]
  /external/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 476 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID));
480 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID));
490 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
AArch64RegisterInfo.cpp 297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
AArch64LoadStoreOptimizer.cpp 649 TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
704 unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
910 TII->getRegClass(MI->getDesc(), 0, TRI, *(MBB.getParent()))
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  /external/llvm/lib/Target/Mips/
MipsOptimizePICCall.cpp 119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
  /external/llvm/include/llvm/CodeGen/
MachineRegisterInfo.h 514 /// constrainRegClass(ToReg, getRegClass(FromReg))
554 /// getRegClass - Return the register class of the specified virtual register.
556 const TargetRegisterClass *getRegClass(unsigned Reg) const {
    [all...]
  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 399 const MCRegisterClass& getRegClass(unsigned i) const {
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 557 /// getRegClass - Returns the register class associated with the enumeration
559 const TargetRegisterClass *getRegClass(unsigned i) const {
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 250 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);

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