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Searched refs:getRegClass (Results 76 - 93 of 93) sorted by null

/external/llvm/lib/Target/Mips/
MipsISelLowering.cpp	`[all...]`
/external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGRRList.cpp	`292 const TargetRegisterClass RC = MF.getRegInfo().getRegClass(Reg); 301 const TargetRegisterClass RC = TRI->getRegClass(DstRCIdx); 309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); [all...]`
SelectionDAGISel.cpp	`569 MRI.constrainRegClass(To, MRI.getRegClass(From)); [all...]`
SelectionDAGBuilder.cpp	`[all...]`
/external/llvm/lib/CodeGen/
TargetLoweringBase.cpp	`[all...]`
/external/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp	`[all...]`
/external/llvm/lib/Target/AArch64/
AArch64FastISel.cpp	`[all...]`
/external/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp	`[all...]`
ARMBaseInstrInfo.cpp	`[all...]`
ARMFastISel.cpp	`[all...]`
/external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp	`[all...]`
/external/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp	`[all...]`
/external/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp	`213 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { [all...]`
PPCISelLowering.cpp	`[all...]`
/external/llvm/utils/TableGen/
CodeGenRegisters.cpp	`[all...]`
/external/llvm/lib/Target/X86/
X86FastISel.cpp	`[all...]`
X86ISelLowering.cpp	`[all...]`
/external/llvm/lib/Target/Sparc/
SparcISelLowering.cpp	`[all...]`

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