| /art/compiler/dex/quick/mips/ |
| call_mips.cc | 27 bool MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
64 void MipsMir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
141 void MipsMir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
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| fp_mips.cc | 210 void MipsMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir,
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| int_mips.cc | 230 void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
234 void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
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| /external/clang/test/SemaCXX/ |
| class.cpp | 70 mutable int &mir; // expected-error {{'mutable' cannot be applied to references}} member in class:C
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| /art/compiler/dex/quick/arm64/ |
| codegen_arm64.h | 185 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE;
186 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE;
187 void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE;
200 void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE;
201 void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE
[all...] |
| int_arm64.cc | 183 void Arm64Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
184 RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
189 RegLocation rl_dest = mir_graph_->GetDest(mir);
192 if (mir->ssa_rep->num_uses == 1) {
194 GenSelect(mir->dalvikInsn.vB, mir->dalvikInsn.vC, mir->meta.ccode, rl_result.reg,
198 RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]];
199 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]]
[all...] |
| call_arm64.cc | 46 void Arm64Mir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
98 void Arm64Mir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
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| /art/compiler/dex/ |
| global_value_numbering_test.cc | 233 mirs_ = reinterpret_cast<MIR*>(cu_.arena.Alloc(sizeof(MIR) * count, kArenaAllocMIR));
237 MIR* mir = &mirs_[i]; local
240 bb->AppendMIR(mir);
241 mir->dalvikInsn.opcode = def->opcode;
242 mir->dalvikInsn.vB = static_cast<int32_t>(def->value);
243 mir->dalvikInsn.vB_wide = def->value;
246 mir->meta.ifield_lowering_info = def->field_info;
249 mir->meta.sfield_lowering_info = def->field_info
[all...] |
| frontend.cc | 583 for (MIR* mir = bb->first_mir_insn; mir != nullptr; mir = mir->next) {
584 int opcode = mir->dalvikInsn.opcode;
588 if (!MIR::DecodedInstruction::IsPseudoMirOp(opcode)) {
590 << mir->dalvikInsn.opcode;
592 VLOG(compiler) << "Unsupported extended MIR opcode : "
603 uint32_t invoke_method_idx = mir->dalvikInsn.vB
[all...] |
| /art/compiler/dex/quick/ |
| gen_common.cc | 531 void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double,
533 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir);
567 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) {
620 void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest,
622 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir);
652 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) {
722 void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size
[all...] |
| codegen_util.cc | [all...] |
| gen_invoke.cc | [all...] |
| /art/compiler/dex/quick/x86/ |
| call_x86.cc | 30 void X86Mir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
63 void X86Mir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) {
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| fp_x86.cc | 493 void X86Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias,
501 rl_src1 = mir_graph_->GetSrcWide(mir, 0);
502 rl_src2 = mir_graph_->GetSrcWide(mir, 2);
507 rl_src1 = mir_graph_->GetSrc(mir, 0);
508 rl_src2 = mir_graph_->GetSrc(mir, 1);
513 ConditionCode ccode = mir->meta.ccode;
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| int_x86.cc | 270 void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
272 RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
273 RegLocation rl_dest = mir_graph_->GetDest(mir);
277 ConditionCode ccode = mir->meta.ccode;
280 const bool is_constant_case = (mir->ssa_rep->num_uses == 1);
283 int true_val = mir->dalvikInsn.vB;
284 int false_val = mir->dalvikInsn.vC;
347 RegLocation rl_true = mir_graph_->GetSrc(mir, 1);
348 RegLocation rl_false = mir_graph_->GetSrc(mir, 2)
[all...] |
| /art/compiler/dex/quick/arm/ |
| int_arm.cc | 230 void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
232 RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
233 RegLocation rl_dest = mir_graph_->GetDest(mir);
238 ConditionCode ccode = mir->meta.ccode;
239 if (mir->ssa_rep->num_uses == 1) {
241 int true_val = mir->dalvikInsn.vB;
242 int false_val = mir->dalvikInsn.vC;
282 RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]];
283 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]]
[all...] |
| call_arm.cc | 46 void ArmMir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
94 void ArmMir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
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