| /external/vixl/src/a64/ |
| macro-assembler-a64.h | 951 void Smull(const Register& rd, const Register& rn, const Register& rm) {
956 smull(rd, rn, rm);
[all...] |
| assembler-a64.cc | 953 void Assembler::smull(const Register& rd, function in class:vixl::Assembler
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm64.cc | 457 COMPARE(smull(x0, w0, w1), "smull x0, w0, w1");
458 COMPARE(smull(lr, w30, w0), "smull lr, w30, w0");
[all...] |
| test-assembler-arm64.cc | 1109 __ Smull(x8, w17, w18);
1110 __ Smull(x9, w18, w18);
1111 __ Smull(x10, w19, w19);
1153 __ Smull(x2, w0, w1);
1161 TEST(smull) {
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| /external/vixl/test/ |
| test-disasm-a64.cc | 418 COMPARE(smull(x0, w0, w1), "smull x0, w0, w1");
419 COMPARE(smull(x30, w30, w0), "smull x30, w30, w0");
[all...] |
| test-assembler-a64.cc | 1048 __ Smull(x8, w17, w18);
1049 __ Smull(x9, w18, w18);
1050 __ Smull(x10, w19, w19);
1092 __ Smull(x2, w0, w1);
1100 TEST(smull) {
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| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_ColorMatrix.S | 46 smull \opd, \opa, \opb
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| /external/chromium_org/v8/src/arm/ |
| full-codegen-arm.cc | [all...] |
| assembler-arm.cc | 1595 void Assembler::smull(Register dstL, function in class:v8::internal::Assembler
[all...] |
| macro-assembler-arm.cc | [all...] |
| /external/llvm/test/MC/ARM/ |
| basic-arm-instructions.s | [all...] |
| basic-thumb2-instructions.s | [all...] |
| /external/chromium_org/v8/src/arm64/ |
| assembler-arm64.cc | 1504 void Assembler::smull(const Register& rd, function in class:v8::internal::Assembler
[all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | [all...] |
| /external/freetype/src/truetype/ |
| ttinterp.c | [all...] |
| /external/valgrind/main/none/tests/arm/ |
| v6media.stdout.exp | 29 SMULL
30 smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
31 smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
32 smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
33 smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
34 smull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
35 smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
[all...] |
