| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 155 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
435 addQRTypeForNEON(MVT::v4i32);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
539 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
567 // It is legal to extload from v4i8 to v4i16 or v4i32.
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 215 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
256 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
|
| MipsSEISelLowering.cpp | 91 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
275 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
[all...] |
| MipsSEISelDAGToDAG.cpp | 801 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
837 ViaVecTy = MVT::v4i32;
|
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 652 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
664 else if (VecVT == MVT::v4i32)
680 else if (VecVT == MVT::v4i32)
695 else if (VecVT == MVT::v4i32)
726 // types (v16i8, v8i16, v4i32, and v4f32).
733 case MVT::v4i32:
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
|
| SIISelLowering.cpp | 37 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 46 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
85 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
101 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
[all...] |
| AMDGPUISelDAGToDAG.cpp | 729 return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32,
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 93 case MVT::v4i32: return "MVT::v4i32";
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
|
| SIISelLowering.cpp | 37 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 62 case MVT::v4i32:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 466 case MVT::v4i32:
[all...] |
