/external/llvm/lib/CodeGen/ |
LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; 199 MachineInstr *Def = PhysRegDef[SubReg]; 204 LastDefReg = SubReg; 252 unsigned SubReg = *SubRegs; 253 if (Processed.count(SubReg)) 255 if (PartDefRegs.count(SubReg)) 259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, 262 PhysRegDef[SubReg] = LastPartialDef; 263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) 291 unsigned SubReg = *SubRegs [all...] |
ExpandPostRAPseudos.cpp | 99 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); 103 DEBUG(dbgs() << "subreg: replaced by: " << *MI); 116 DEBUG(dbgs() << "subreg: replace by: " << *MI); 119 DEBUG(dbgs() << "subreg: eliminated!"); 128 DEBUG(dbgs() << "subreg: " << *CopyMI);
|
PeepholeOptimizer.cpp | 256 /// result, then replace all reachable uses of the source with the subreg of the 450 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg) 792 // If we look for a different subreg, it means we want a subreg of src. 793 // Bails as we do not support composing subreg yet. 813 // If we look for a different subreg, it means we want a subreg of the src. 814 // Bails as we do not support composing subreg yet. 838 // If we are composing subreg, bails out. 839 // The case we are checking is Def.<subreg> = REG_SEQUENCE [all...] |
MachineInstrBundle.cpp | 175 unsigned SubReg = *SubRegs; 176 if (LocalDefSet.insert(SubReg)) 177 LocalDefs.push_back(SubReg);
|
RegisterCoalescer.h | 89 /// the full register, but was a subreg operation.
|
/external/llvm/lib/MC/ |
MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { 39 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); 44 if (*Subs == SubReg)
|
/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.td | 36 class GP8<GPR SubReg, string n> : PPCReg<n> { 37 let HWEncoding = SubReg.HWEncoding; 38 let SubRegs = [SubReg]; 60 class VR<VF SubReg, string n> : PPCReg<n> { 61 let HWEncoding{4-0} = SubReg.HWEncoding{4-0}; 63 let SubRegs = [SubReg]; 69 class VSRL<FPR SubReg, string n> : PPCReg<n> { 70 let HWEncoding = SubReg.HWEncoding; 71 let SubRegs = [SubReg]; 77 class VSRH<VR SubReg, string n> : PPCReg<n> [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb2ITBlockPass.cpp | 78 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); 79 Subreg.isValid(); ++Subreg) 80 Uses.insert(*Subreg); 85 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); 86 Subreg.isValid(); ++Subreg) 87 Defs.insert(*Subreg);
|
A15SDOptimizer.cpp | 152 // Get the subreg type that is most likely to be coalesced 265 // a subreg copy of a DPR, just use that DPR. 268 // Is it a subreg copy of ssub_0? 271 DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI); 273 // Find the thing we're subreg copying out of - is it of the same 279 DEBUG(dbgs() << "Subreg copy is compatible - returning "); 535 // DPair has the same length as QPR and also has two DPRs as subreg.
|
/external/llvm/lib/Target/R600/ |
SIFixSGPRCopies.cpp | 90 unsigned SubReg) const; 94 unsigned SubReg) const; 137 unsigned SubReg) const { 144 RC = TRI->getSubRegClass(RC, SubReg); 163 unsigned SubReg) const { 166 return TRI->getSubRegClass(RC, SubReg); 170 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
|
SILowerControlFlow.cpp | 407 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0); 408 if (!SubReg) 409 SubReg = Vec; 413 .addReg(SubReg + Off) 428 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0); 429 if (!SubReg) 430 SubReg = Dst; 434 .addReg(SubReg + Off, RegState::Define)
|
R600OptimizeVectorRegisters.cpp | 12 /// common data and/or have enough undef subreg using swizzle abilities. 191 unsigned SubReg = (*It).first; 198 .addReg(SubReg) 200 UpdatedRegToChan[SubReg] = Chan;
|
SIRegisterInfo.h | 59 /// SubReg index.
|
SIInstrInfo.cpp | 328 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(), 334 .addReg(SubReg) 352 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(), 356 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg) 396 unsigned SubReg = MI->getOperand(1).getSubReg(); 399 MI->getOperand(2).setSubReg(SubReg); 788 unsigned SubReg = MRI.createVirtualRegister(SubRC); 791 // value so we don't need to worry about merging its subreg index with the 799 SubReg) 801 return SubReg; [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64AdvSIMDScalarPass.cpp | 100 static bool isGPR64(unsigned Reg, unsigned SubReg, 102 if (SubReg) 109 static bool isFPR64(unsigned Reg, unsigned SubReg, 113 SubReg == 0) || 115 SubReg == AArch64::dsub); 117 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || 118 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); 125 unsigned &SubReg) { 126 SubReg = 0; 134 SubReg = AArch64::dsub [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZRegisterInfo.h | 22 // Return the subreg to use for referring to the even and odd registers
|
SystemZElimCompare.cpp | 107 // Return true if any CC result of MI would reflect the value of subreg 108 // SubReg of Reg. 109 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) { 114 MI->getOperand(0).getSubReg() == SubReg) 131 MI->getOperand(1).getSubReg() == SubReg)
|
/external/llvm/test/CodeGen/X86/ |
2011-02-21-VirtRegRewriter-KillSubReg.ll | 3 ; `KillOps[*SR] == KillOp && "invalid subreg kill flags"'
|
/external/llvm/include/llvm/CodeGen/ |
MachineOperand.h | 71 /// MO_Register has no subReg. 344 void setSubReg(unsigned subReg) { 346 SubReg_TargetFlags = subReg; 347 assert(SubReg_TargetFlags == subReg && "SubReg out of range"); 351 /// subregister Reg:SubReg. Take any existing SubReg index into account, 352 /// using TargetRegisterInfo to compose the subreg indices if necessary. 358 /// Reg, taking any existing SubReg into account. For instance, 580 unsigned SubReg = 0 [all...] |
/external/llvm/include/llvm/Target/ |
TargetRegisterInfo.h | 224 const char *const *SubRegIndexNames; // Names of subreg indexes. 496 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 501 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. [all...] |
TargetOpcodes.h | 76 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
|
/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
rtl.h | 277 1 in a SUBREG used for SUBREG_PROMOTED_UNSIGNED_P. 292 1 in a SUBREG used for SUBREG_PROMOTED_UNSIGNED_P. 301 1 in a SUBREG expression if was generated from a variable with a [all...] |
/external/clang/lib/StaticAnalyzer/Checkers/ |
ArrayBoundCheckerV2.cpp | 276 if (const SubRegion *subReg = dyn_cast<SubRegion>(region)) { 279 return RegionRawOffsetV2(subReg, offset);
|
/external/llvm/include/llvm/MC/ |
MCRegisterInfo.h | 148 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg 165 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 167 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered 169 unsigned NumSubRegIndices; // Number of subreg indices.
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.h | 90 /// EmitSubregNode - Generate machine code for subreg nodes.
|