/external/llvm/test/MC/AArch64/ |
arm64-diags.s | 77 ldrb w1, [x3, w3, sxtw #4] 78 ldrh w1, [x3, w3, sxtw #4] 79 ldr w1, [x3, w3, sxtw #4] 80 ldr x1, [x3, w3, sxtw #4] 81 ldr b1, [x3, w3, sxtw #4] 82 ldr h1, [x3, w3, sxtw #4] 83 ldr s1, [x3, w3, sxtw #4] 84 ldr d1, [x3, w3, sxtw #4] 85 ldr q1, [x3, w3, sxtw #1] 87 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of # [all...] |
arm64-arithmetic-encoding.s | 176 add w1, w2, w3, sxtw 185 ; CHECK: add w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x0b] 193 add x1, x2, w3, sxtw 200 ; CHECK: add x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x8b] 220 sub w1, w2, w3, sxtw 229 ; CHECK: sub w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x4b] 237 sub x1, x2, w3, sxtw 244 ; CHECK: sub x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xcb] 264 adds w1, w2, w3, sxtw 273 ; CHECK: adds w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x2b [all...] |
/system/core/libpixelflinger/tests/arch-arm64/disassembler/ |
arm64_diassembler_test.cpp | 159 { 0xb87ed80f, "ldr w15, [x0, w30, sxtw #2]" }, 160 { 0xb86fc9fe, "ldr w30, [x15, w15, sxtw #0]" }, 168 { 0xb83ed80f, "str w15, [x0, w30, sxtw #2]" }, 169 { 0xb82fc9fe, "str w30, [x15, w15, sxtw #0]" }, 177 { 0x787ed80f, "ldrh w15, [x0, w30, sxtw #1]" }, 178 { 0x786fc9fe, "ldrh w30, [x15, w15, sxtw #0]" }, 186 { 0x783ed80f, "strh w15, [x0, w30, sxtw #1]" }, 187 { 0x782fc9fe, "strh w30, [x15, w15, sxtw #0]" }, 195 { 0x387ec80f, "ldrb w15, [x0, w30, sxtw ]" }, 196 { 0x386fd9fe, "ldrb w30, [x15, w15, sxtw #0]" } [all...] |
/external/llvm/test/CodeGen/Hexagon/ |
extload-combine.ll | 30 ; CHECK: sxtw([[VAR1]]) 52 ; CHECK: sxtw([[VAR3]]) 74 ; CHECK: sxtw([[VAR5]])
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/external/llvm/test/CodeGen/AArch64/ |
arm64-coalesce-ext.ll | 10 ; CHECK: sxtw x[[EXT:[0-9]+]], w[[SUM]]
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arm64-extend.ll | 8 ; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
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ldst-regoffset.ll | 19 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw] 47 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #1] 71 ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw] 100 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2] 124 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] 152 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3] 174 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] 200 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2] 224 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] 253 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3 [all...] |
arm64-trunc-store.ll | 25 ; CHECK-NEXT: str w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #2] 45 ; CHECK-NEXT: strh w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #1] 63 ; CHECK-NEXT: add [[ADDR:x[0-9]+]], [[BASEADDR]], w0, sxtw
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arm64-addr-type-promotion.ll | 14 ; CHECK-NEXT: ldrb [[BLOCKVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE]], w0, sxtw] 15 ; CHECK-NEXT: ldrb [[BLOCKVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE]], w1, sxtw] 19 ; CHECK: add [[BLOCKBASE2:x[0-9]+]], [[BLOCKBASE]], w1, sxtw 20 ; CHECK-NEXT: add [[BLOCKBASE1:x[0-9]+]], [[BLOCKBASE]], w0, sxtw
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arm64-atomic.ll | 125 ; CHECK: ldrb {{w[0-9]+}}, [x0, w1, sxtw] 150 ; CHECK: ldrh {{w[0-9]+}}, [x0, w1, sxtw #1] 175 ; CHECK: ldr {{w[0-9]+}}, [x0, w1, sxtw #2] 200 ; CHECK: ldr {{x[0-9]+}}, [x0, w1, sxtw #3] 232 ; CHECK: strb {{w[0-9]+}}, [x0, w1, sxtw] 254 ; CHECK: strh {{w[0-9]+}}, [x0, w1, sxtw #1] 276 ; CHECK: str {{w[0-9]+}}, [x0, w1, sxtw #2] 298 ; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3]
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arm64-register-offset-addressing.ll | 25 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] 60 ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] 95 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] 128 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
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f16-convert.ll | 28 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, w1, sxtw #1] 41 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, w1, sxtw #1] 154 ; CHECK-NEXT: str h0, [x0, w1, sxtw #1] 167 ; CHECK-NEXT: str h0, [x0, w1, sxtw #1]
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/external/libhevc/common/arm64/ |
ihevc_deblk_chroma_vert.s | 62 sxtw x4,w4 63 sxtw x5,w5 64 sxtw x6,w6 98 sxtw x3,w3 114 sxtw x2,w2 147 sxtw x3,w3 163 sxtw x2,w2
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ihevc_deblk_chroma_horz.s | 61 sxtw x4,w4 62 sxtw x5,w5 63 sxtw x6,w6 65 sxtw x9,w9
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ihevc_intra_pred_filters_luma_mode_11_to_17.s | 124 sxtw x7,w7 128 sxtw x8,w8 141 sxtw x11,w11 146 sxtw x12,w12 148 sxtw x10,w10 150 sxtw x14,w14 153 sxtw x11,w11 155 sxtw x12,w12 157 sxtw x10,w10 159 sxtw x14,w1 [all...] |
ihevc_intra_pred_filters_luma_mode_19_to_25.s | 124 sxtw x7,w7 128 sxtw x8,w8 182 sxtw x11,w11 184 sxtw x11,w11 207 sxtw x11,w11 210 sxtw x11,w11 226 sxtw x9,w9 266 sxtw x14,w14 312 sxtw x14,w14 389 sxtw x14,w1 [all...] |
ihevc_weighted_pred_bi.s | 158 sxtw x8,w8 159 sxtw x9,w9 160 sxtw x10,w10 161 sxtw x11,w11 162 sxtw x12,w12
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ihevc_intra_pred_chroma_planar.s | 130 sxtw x7,w7 139 sxtw x7,w7 186 sxtw x7,w7 189 sxtw x11,w11 200 sxtw x7,w7 252 sxtw x11,w11 348 sxtw x7,w7
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/external/libhevc/decoder/arm64/ |
ihevcd_fmt_conv_420sp_to_420p.s | 96 sxtw x5,w5 103 sxtw x5,w5 144 sxtw x5,w5 146 sxtw x7,w7 158 sxtw x4,w4
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ihevcd_fmt_conv_420sp_to_420sp.s | 98 sxtw x5,w5 154 sxtw x5,w5
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/external/chromium_org/v8/src/arm64/ |
regexp-macro-assembler-arm64.cc | 220 __ Add(x10, input_end(), Operand(current_input_offset(), SXTW)); 231 __ Add(x10, input_end(), Operand(current_input_offset(), SXTW)); 257 Operand(current_input_offset(), SXTW)); 321 Operand(capture_start_offset, SXTW)); 324 Operand(capture_length, SXTW)); 327 Operand(current_input_offset(), SXTW)); 362 __ Cmp(current_input_offset().X(), Operand(current_input_offset(), SXTW)); 384 __ Add(x0, input_end(), Operand(capture_start_offset, SXTW)); 388 __ Add(x1, input_end(), Operand(current_input_offset(), SXTW)); 440 __ Add(capture_start_address, input_end(), Operand(w10, SXTW)); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 11 // %vreg170<def> = SXTW %vreg166 31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill> 137 // %vreg170<def> = SXTW %vreg166 138 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) { 148 // %vreg170<def> = SXTW %vreg166
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/external/chromium_org/v8/test/cctest/ |
test-disasm-arm64.cc | 125 COMPARE(dci(0x93407c00), "sxtw x0, w0"); 145 COMPARE(Mov(x16, Operand(x20, SXTW, 3)), "sbfiz x16, x20, #3, #32"); 385 COMPARE(add(x24, x25, Operand(x26, SXTW, 1)), "add x24, x25, w26, sxtw #1"); 411 COMPARE(sub(x24, x25, Operand(x26, SXTW, 1)), "sub x24, x25, w26, sxtw #1"); 522 COMPARE(sxtw(x8, x9), "sxtw x8, w9"); 525 COMPARE(sxtw(x4, w5), "sxtw x4, w5") [all...] |
/external/vixl/test/ |
test-disasm-a64.cc | 101 COMPARE(dci(0x93407c00), "sxtw x0, w0"); 120 COMPARE(Mov(x16, Operand(x17, SXTW, 3)), "sbfiz x16, x17, #3, #32"); 346 COMPARE(add(x24, x25, Operand(x26, SXTW, 1)), "add x24, x25, w26, sxtw #1"); 372 COMPARE(sub(x24, x25, Operand(x26, SXTW, 1)), "sub x24, x25, w26, sxtw #1"); 491 COMPARE(sxtw(x8, x9), "sxtw x8, w9"); 494 COMPARE(sxtw(x4, w5), "sxtw x4, w5") [all...] |
/external/vixl/doc/ |
changelog.md | 35 + Fixed sign extension for W->X conversions using `sxtb`, `sxth` and `sxtw`.
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