/system/core/libpixelflinger/tests/arch-arm64/disassembler/ |
arm64_diassembler_test.cpp | 158 { 0xb87f4be0, "ldr w0, [sp, wzr, uxtw #0]" }, 161 { 0xb8605bdf, "ldr wzr, [x30, w0, uxtw #2]" }, 167 { 0xb83f4be0, "str w0, [sp, wzr, uxtw #0]" }, 170 { 0xb8205bdf, "str wzr, [x30, w0, uxtw #2]" }, 176 { 0x787f4be0, "ldrh w0, [sp, wzr, uxtw #0]" }, 179 { 0x78605bdf, "ldrh wzr, [x30, w0, uxtw #1]" }, 185 { 0x783f4be0, "strh w0, [sp, wzr, uxtw #0]" }, 188 { 0x78205bdf, "strh wzr, [x30, w0, uxtw #1]" }, 194 { 0x387f5be0, "ldrb w0, [sp, wzr, uxtw #0]" }, 197 { 0x38604bdf, "ldrb wzr, [x30, w0, uxtw ]" }, [all...] |
/external/llvm/test/CodeGen/AArch64/ |
arm64-register-offset-addressing.ll | 34 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] 50 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] 71 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1] 85 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] 105 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2] 119 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] 138 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3]
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ldst-regoffset.ll | 34 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 62 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 90 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #1] 114 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 142 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2] 166 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 190 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3] 215 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 242 ; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2] 268 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] [all...] |
addsub_ext.ll | 158 ; N.b. we could probably check more here ("add w2, w3, w1, uxtw" for 171 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw 176 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
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arm64-addr-mode-folding.ll | 128 ; CHECK-NOT: , uxtw #2] 151 ; CHECK: , uxtw #2] 152 ; CHECK: , uxtw #2]
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arm64-ldxr-stxr.ll | 66 ; CHECK-NOT: uxtw 115 ; CHECK-NOT: uxtw 203 ; CHECK-NOT: uxtw 252 ; CHECK-NOT: uxtw
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arm64-arith.ll | 138 ; CHECK: add x0, x1, w0, uxtw
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/external/llvm/test/MC/AArch64/ |
arm64-arithmetic-encoding.s | 172 add w1, w2, w3, uxtw 181 ; CHECK: add w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x0b] 190 add x1, x2, w3, uxtw 197 ; CHECK: add x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x8b] 203 add w1, wsp, w3, uxtw #0 216 sub w1, w2, w3, uxtw 225 ; CHECK: sub w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x4b] 234 sub x1, x2, w3, uxtw 241 ; CHECK: sub x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xcb] 247 sub w1, wsp, w3, uxtw # [all...] |
arm64-diags.s | 87 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 90 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1 93 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2 96 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 99 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 102 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1 105 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2 108 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 111 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 116 ; registers when using uxtw/sxtw extends. Everything else requires a 64-bi [all...] |
basic-a64-instructions.s | 20 add x12, x1, w20, uxtw 28 // CHECK: add x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0x8b] 38 add w30, w29, wzr, uxtw 46 // CHECK: add w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x0b] 56 add w17, w19, w23, uxtw #2 60 // CHECK: add w17, w19, w23, uxtw #2 // encoding: [0x71,0x4a,0x37,0x0b] 66 sub x12, x1, w20, uxtw 74 // CHECK: sub x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xcb] 83 sub w30, w29, wzr, uxtw 91 // CHECK: sub w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x4b [all...] |
basic-a64-diagnostics.s | [all...] |
/external/chromium_org/v8/test/cctest/ |
test-disasm-arm64.cc | 380 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); 392 COMPARE(add(wcsp, wcsp, Operand(w4, UXTW, 2)), "add wcsp, wcsp, w4, lsl #2"); 406 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); 418 COMPARE(sub(wcsp, wcsp, Operand(w4, UXTW, 2)), "sub wcsp, wcsp, w4, lsl #2"); 531 COMPARE(uxtw(x18, x19), "ubfx x18, x19, #0, #32"); [all...] |
/external/vixl/test/ |
test-disasm-a64.cc | 341 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); 353 COMPARE(add(wsp, wsp, Operand(w4, UXTW, 2)), "add wsp, wsp, w4, lsl #2"); 367 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); 379 COMPARE(sub(wsp, wsp, Operand(w4, UXTW, 2)), "sub wsp, wsp, w4, lsl #2"); 500 COMPARE(uxtw(x18, x19), "ubfx x18, x19, #0, #32"); [all...] |
test-simulator-a64.cc | 202 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); 306 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 310 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 425 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 429 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 433 __ Ldr(fa, MemOperand(inputs_base, index_a, UXTW, index_shift)); 555 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 559 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 679 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 792 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)) [all...] |
/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
AArch64AddressingModes.h | 42 UXTW, 62 case AArch64_AM::UXTW: return "uxtw"; 129 case 2: return AArch64_AM::UXTW; 145 /// 010 ==> uxtw 156 case AArch64_AM::UXTW: return 2; break; 192 /// 010 ==> uxtw
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/external/llvm/test/MC/Disassembler/AArch64/ |
arm64-arithmetic.txt | 191 # CHECK: add x1, x2, w3, uxtw 233 # CHECK: sub x1, x2, w3, uxtw 275 # CHECK: adds x1, x2, w3, uxtw 313 # CHECK: subs x1, x2, w3, uxtw 329 # CHECK: cmp x8, w8, uxtw 330 # CHECK: cmp w9, w8, uxtw
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arm64-memory.txt | 101 # CHECK: strb w0, [x0, w0, uxtw] 429 # CHECK: str h0, [x0, w0, uxtw] 431 # CHECK: str d1, [sp, w3, uxtw #3] 433 # CHECK: str q1, [sp, w3, uxtw #4]
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/system/core/libpixelflinger/codeflinger/ |
Arm64Disassembler.cpp | 205 "reserved","reserved","uxtw", "lsl", 214 "uxtb","uxth","uxtw","uxtx",
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/external/chromium_org/v8/src/arm64/ |
disasm-arm64.cc | [all...] |
assembler-arm64-inl.h | 392 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); 475 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); 528 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); [all...] |
regexp-macro-assembler-arm64.cc | 194 __ Add(x10, code_pointer(), Operand(w10, UXTW)); 539 __ Ldrb(w11, MemOperand(x11, w10, UXTW)); 620 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); 633 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); [all...] |
/external/vixl/src/a64/ |
disasm-a64.cc | [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | 953 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || 988 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && [all...] |
/frameworks/rs/cpu_ref/ |
rsCpuIntrinsics_advsimd_Blend.S | 594 ldrsh x6, [x5, w2, uxtw #1] 595 add x0, x0, w3, uxtw #2 596 add x1, x1, w3, uxtw #2
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/external/vixl/doc/ |
supported-instructions.md | 999 ### uxtw ### 1003 inline void uxtw(const Register& rd, const Register& rn)
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