Search

Home	Sort by relevance Sort by last modified time

Searched full:_fpecode (Results 1 - 3 of 3) sorted by null

/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/
float.h	`269 #define _fpecode (*(__fpecode())) macro`
/prebuilts/gcc/darwin-x86/arm/arm-eabi-4.8/lib/
libarm-linux-android-sim.a	4 __.SYMDEF SORTED??0"z8?8?8?8?8?:%?8?K?\??0r?0r?0"?0"dhfu(I?0"?8?8?8?888&848B8H 8-?:Q8?:?:?:?:?:?:\8g8 ::?0"r8?0"?8?7?7)?7<?7J?7?8-:@:P:?0"?8`:t:?8?0"?8?8?8?8?8?:?:?:?:88?:?:+8?b=8I8?::[8+8U98UH8U^8Uu8U?8U??????????????????????????? ?? ?? ??# ??\ 8-h8s 8-~ 8-? 8-? 8-? 8-:? 8-t8m??????8U??L!8_48_F8_1?LZw?L???^?7g?7?8U, ???????0r?0r?0r0r"0r60r@0r?J0rT0r^0rj0r}0r?0r?0r?0r?0r?0r?0r0r0r?Lp?7[?d? _cb_host_to_target_errno_cb_host_to_target_stat_cb_is_stderr_cb_is_stdin_cb_is_stdout_cb_read_target_syscall_maps_cb_store_target_endian_cb_target_to_host_open_cb_target_to_host_syscall_default_callback_sim_cb_eprintf_sim_cb_printf_cb_get_string_cb_syscall_simulator_sysroot_cb_init_errno_map_cb_init_open_map_cb_init_syscall_map_version_ARMul_Emulate26_ARMul_Emulate32_ARMul_Abort_ARMul_DoInstr_ARMul_DoProg_ARMul_EmulateInit_ARMul_MultTable_ARMul_NewState_ARMul_Reset_ARMul_SelectProcessor_ARMul_OSException_ARMul_OSExit_ARMul_OSHandleSWI_ARMul_OSInit_ARMul_OSLastErrorP_fpecode_fpesize_swi_mask_ARMul_AddCarry_ARMul_AddOverflow_ARMul_Align_ARMul_CDP_ARMul_CPSRAltered_ARMul_EnvokeEvent_ARMul_FixCPSR_ARMul_FixSPSR_ARMul_GetCPSR_ARMul_GetNextPC_ARMul_GetPC_ARMul_GetR15_ARMul_GetReg_ARMul_GetSPSR_ARMul_LDC_ARMul_MCR_ARMul_MRC_ARMul_NegZero_ARMul_NthReg_ARMul_R15Altered_ARMul_STC_ARMul_ScheduleEvent_ARMul_SetCPSR_ARMul_SetPC_ARMul_SetR15_ARMul_SetReg_ARMul_SetSPSR_ARMul_SubCarry_ARMul_SubOverflow_ARMul_SwitchMode_ARMul_Time_ARMul_UndefInstr_AddOverflow_IntPending_SubOverflow_ARMul_Ccycles_ARMul_Icycles_ARMul_LoadByte_ARMul_LoadHalfWord_ARMul_LoadInstrN_ARMul_LoadInstrS_ARMul_LoadWordN_ARMul_LoadWordS_ARMul_MemoryExit_ARMul_MemoryInit_ARMul_ReLoadInstr_ARMul_ReadByte_ARMul_ReadWord_ARMul_SafeReadByte_ARMul_SafeWriteByte_ARMul_StoreByte_ARMul_StoreHalfWord_ARMul_StoreWordN_ARMul_StoreWordS_ARMul_SwapByte_ARMul_SwapWord_ARMul_WriteByte_ARMul_WriteWord_SWI_vector_installed_BAG_getfirst_BAG_getsecond_BAG_killpair_byfirst_BAG_killpair_bysecond_BAG_newbag_BAG_putpair_addtolist_killwholelist_ARMul_ThumbDecode_ARMul_ConsolePrint_ARMul_Debug_sim_close_sim_complete_command_sim_create_inferior_sim_do_command_sim_fetch_register_sim_info_sim_load_sim_open_sim_read_sim_resume_sim_set_callbacks_sim_set_verbose_sim_size_sim_stop_sim_stop_reason_sim_store_register_sim_target_display_usage_sim_target_parse_command_line_sim_trace_sim_write_sim_load_file_ARMul_CoProAttach_ARMul_CoProDetach_ARMul_CoProExit_ARMul_CoProInit_XScale_check_memacc_XScale_debug_moe_XScale_set_fsr_far_read_cp15_reg_DSPCDP4_DSPCDP5_DSPCDP6_DSPLDC4_DSPLDC5_DSPMCR4_DSPMCR5_DSPMCR6_DSPMRC4_DSPMRC5_DSPMRC6_DSPSTC4_DSPSTC5_mv_compute_host_endianness_ARMul_HandleIwmmxt_Fetch_Iwmmxt_Register_IwmmxtCDP_IwmmxtLDC_IwmmxtMCR_IwmmxtMRC_IwmmxtSTC_Store_Iwmmxt_Register#1/20 1383608922 501 0 100644 15676 ` [all...]
/prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.8/lib/
libarm-linux-android-sim.a	4 __.SYMDEF SORTED??0"z8?8?8?8?8?:%?8?K?\??0r?0r?0"?0"dhfu(I?0"?8?8?8?888&848B8H 8-?:Q8?:?:?:?:?:?:\8g8 ::?0"r8?0"?8?7?7)?7<?7J?7?8-:@:P:?0"?8`:t:?8?0"?8?8?8?8?8?:?:?:?:88?:?:+8?b=8I8?::[8+8U98UH8U^8Uu8U?8U??????????????????????????? ?? ?? ??# ??\ 8-h8s 8-~ 8-? 8-? 8-? 8-:? 8-t8m??????8U??L!8_48_F8_1?LZw?L???^?7g?7?8U, ???????0r?0r?0r0r"0r60r@0r?J0rT0r^0rj0r}0r?0r?0r?0r?0r?0r?0r0r0r?Lp?7[?d? _cb_host_to_target_errno_cb_host_to_target_stat_cb_is_stderr_cb_is_stdin_cb_is_stdout_cb_read_target_syscall_maps_cb_store_target_endian_cb_target_to_host_open_cb_target_to_host_syscall_default_callback_sim_cb_eprintf_sim_cb_printf_cb_get_string_cb_syscall_simulator_sysroot_cb_init_errno_map_cb_init_open_map_cb_init_syscall_map_version_ARMul_Emulate26_ARMul_Emulate32_ARMul_Abort_ARMul_DoInstr_ARMul_DoProg_ARMul_EmulateInit_ARMul_MultTable_ARMul_NewState_ARMul_Reset_ARMul_SelectProcessor_ARMul_OSException_ARMul_OSExit_ARMul_OSHandleSWI_ARMul_OSInit_ARMul_OSLastErrorP_fpecode_fpesize_swi_mask_ARMul_AddCarry_ARMul_AddOverflow_ARMul_Align_ARMul_CDP_ARMul_CPSRAltered_ARMul_EnvokeEvent_ARMul_FixCPSR_ARMul_FixSPSR_ARMul_GetCPSR_ARMul_GetNextPC_ARMul_GetPC_ARMul_GetR15_ARMul_GetReg_ARMul_GetSPSR_ARMul_LDC_ARMul_MCR_ARMul_MRC_ARMul_NegZero_ARMul_NthReg_ARMul_R15Altered_ARMul_STC_ARMul_ScheduleEvent_ARMul_SetCPSR_ARMul_SetPC_ARMul_SetR15_ARMul_SetReg_ARMul_SetSPSR_ARMul_SubCarry_ARMul_SubOverflow_ARMul_SwitchMode_ARMul_Time_ARMul_UndefInstr_AddOverflow_IntPending_SubOverflow_ARMul_Ccycles_ARMul_Icycles_ARMul_LoadByte_ARMul_LoadHalfWord_ARMul_LoadInstrN_ARMul_LoadInstrS_ARMul_LoadWordN_ARMul_LoadWordS_ARMul_MemoryExit_ARMul_MemoryInit_ARMul_ReLoadInstr_ARMul_ReadByte_ARMul_ReadWord_ARMul_SafeReadByte_ARMul_SafeWriteByte_ARMul_StoreByte_ARMul_StoreHalfWord_ARMul_StoreWordN_ARMul_StoreWordS_ARMul_SwapByte_ARMul_SwapWord_ARMul_WriteByte_ARMul_WriteWord_SWI_vector_installed_BAG_getfirst_BAG_getsecond_BAG_killpair_byfirst_BAG_killpair_bysecond_BAG_newbag_BAG_putpair_addtolist_killwholelist_ARMul_ThumbDecode_ARMul_ConsolePrint_ARMul_Debug_sim_close_sim_complete_command_sim_create_inferior_sim_do_command_sim_fetch_register_sim_info_sim_load_sim_open_sim_read_sim_resume_sim_set_callbacks_sim_set_verbose_sim_size_sim_stop_sim_stop_reason_sim_store_register_sim_target_display_usage_sim_target_parse_command_line_sim_trace_sim_write_sim_load_file_ARMul_CoProAttach_ARMul_CoProDetach_ARMul_CoProExit_ARMul_CoProInit_XScale_check_memacc_XScale_debug_moe_XScale_set_fsr_far_read_cp15_reg_DSPCDP4_DSPCDP5_DSPCDP6_DSPLDC4_DSPLDC5_DSPMCR4_DSPMCR5_DSPMCR6_DSPMRC4_DSPMRC5_DSPMRC6_DSPSTC4_DSPSTC5_mv_compute_host_endianness_ARMul_HandleIwmmxt_Fetch_Iwmmxt_Register_IwmmxtCDP_IwmmxtLDC_IwmmxtMCR_IwmmxtMRC_IwmmxtSTC_Store_Iwmmxt_Register#1/20 1377060876 501 0 100644 15676 ` [all...]

Completed in 313 milliseconds