| /external/llvm/test/CodeGen/AArch64/ |
| adc.ll | 9 ; CHECK-LE-NEXT: adcs [[ADDHI:x[0-9]+]], x1, x3
11 ; CHECK-BE-NEXT: adcs [[ADDHI:x[0-9]+]], x0, x2
28 ; CHECK-LE: adcs x1, x1, {{x[0-9]|xzr}}
30 ; CHECK-BE: adcs x0, x0, {{x[0-9]|xzr}}
43 ; CHECK-LE: adcs x1, x1, {{x[0-9]}}
45 ; CHECK-BE: adcs x0, x0, {{x[0-9]}}
59 ; CHECK-LE: adcs x1, x1, {{x[0-9]}}
61 ; CHECK-BE: adcs x0, x0, {{x[0-9]}}
|
| nzcv-save.ll | 6 ; DAG ends up with two uses for the flags from an ADCS node, which means they
|
| arm64-atomic-128.ll | 60 ; CHECK: adcs [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-add6.ll | 6 ; CHECK: adcs r1, r3
|
| carry.ll | 16 ; CHECK: adcs r1, r1
|
| /external/valgrind/main/none/tests/arm/ |
| v6intThumb.c | 434 TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0);
435 TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1);
781 TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
782 TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
783 TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
784 TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
[all...] |
| v6intThumb.stdout.exp | 285 ADCS-16 0x105
286 adcs r1, r2 :: rd 0x5859704f rm 0x27181728, c:v-in 0, cpsr 0x00000000
287 adcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
288 adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
289 adcs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
290 adcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
291 adcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
292 adcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
293 adcs r1, r2 :: rd 0x5859704f rm 0x27181728, c:v-in 1, cpsr 0x00000000
294 adcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000 Z
[all...] |
| v6intARM.c | 176 TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0);
177 TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1);
493 TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
494 TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
495 TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
496 TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
[all...] |
| v6intARM.stdout.exp | 35 adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
36 adcs r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, carryin 1, cpsr 0x00000000
[all...] |
| /external/llvm/test/MC/ARM/ |
| thumb2-narrow-dp.ll | 396 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
397 ADCS r5, r5, r1 // Should choose narrow
398 ADCS r3, r1, r3 // Should choose narrow - commutative
399 ADCS.W r2, r2, r1 // Explicitly wide
400 ADCS.W r3, r1, r3
402 ADCS r7, r7, r1 // Should use narrow
403 ADCS r7, r1, r7 // Commutative
404 ADCS r8, r1, r8 // high registers so must use wide encoding
405 ADCS r8, r8, r1
406 ADCS r5, r8, r
[all...] |
| /external/llvm/test/MC/AArch64/ |
| arm64-arithmetic-encoding.s | 10 adcs w5, w4, w3
11 adcs x5, x4, x3
15 ; CHECK: adcs w5, w4, w3 ; encoding: [0x85,0x00,0x03,0x3a]
16 ; CHECK: adcs x5, x4, x3 ; encoding: [0x85,0x00,0x03,0xba]
|
| basic-a64-diagnostics.s | 619 adcs wsp, w3, w5
620 adcs w1, wsp, w2
621 adcs w0, w10, wsp
623 // CHECK-ERROR-NEXT: adcs wsp, w3, w5
626 // CHECK-ERROR-NEXT: adcs w1, wsp, w2
629 // CHECK-ERROR-NEXT: adcs w0, w10, wsp
632 adcs sp, x3, x5
633 adcs x1, sp, x2
634 adcs x0, x10, sp
636 // CHECK-ERROR-NEXT: adcs sp, x3, x
[all...] |
| basic-a64-instructions.s | [all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| arm-tests.txt | 299 # CHECK-NOT: adcs r10, r8, r0, asr #6
|
| thumb-tests.txt | 6 # CHECK: adcs r0, r0, #1
|
| /external/vixl/doc/ |
| supported-instructions.md | 21 ### adcs ###
25 void adcs(const Register& rd,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 56 ADCS,
|
| /external/llvm/lib/Target/ARM/ |
| README-Thumb.txt | 261 when it could use subs + adcs. This is GCC PR46975.
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-arithmetic.txt | 14 # CHECK: adcs w5, w4, w3
15 # CHECK: adcs x5, x4, x3
|
| basic-a64-instructions.txt | 519 # CHECK: adcs w29, w27, w25
520 # CHECK: adcs wzr, w3, w4
521 # CHECK: adcs w9, wzr, w10
522 # CHECK: adcs w20, w0, wzr
528 # CHECK: adcs x29, x27, x25
529 # CHECK: adcs xzr, x3, x4
530 # CHECK: adcs x9, xzr, x10
531 # CHECK: adcs x20, x0, xzr
[all...] |
| /system/keymaster/ |
| ocb.c | 316 "adcs %H1,%H1,%H1\n\t"
317 "adcs %0,%0,%0\n\t"
318 "adcs %H0,%H0,%H0\n\t"
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm64.cc | 431 COMPARE(adcs(w6, w7, Operand(w8)), "adcs w6, w7, w8");
432 COMPARE(adcs(x9, x10, Operand(x11)), "adcs x9, x10, x11");
[all...] |
| test-disasm-arm.cc | 153 "e0bd500c adcs r5, sp, ip");
[all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | 392 COMPARE(adcs(w6, w7, Operand(w8)), "adcs w6, w7, w8");
393 COMPARE(adcs(x9, x10, Operand(x11)), "adcs x9, x10, x11");
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeARM_T2_32.c | 88 #define ADCS 0x4140
737 return push_inst16(compiler, ADCS | RD3(dst) | RN3(arg2));
[all...] |
