| /external/llvm/test/CodeGen/AArch64/ |
| arm64-early-ifcvt.ll | 42 ; CHECK-NEXT: csinc w0, w1, w0, eq
60 ; CHECK-NEXT: csinc x0, x1, x0, eq
78 ; CHECK-NEXT: csinc w0, w1, w0, ne
96 ; CHECK-NEXT: csinc x0, x1, x0, ne
396 ; This function from 175.vpr folds an ADDWri into a CSINC.
|
| cond-sel.ll | 67 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], [[RHS]], ls
75 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
84 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
92 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
181 ; N.b. code is not optimal here (32-bit csinc would be better) but
|
| /bionic/libc/arch-arm64/bionic/ |
| _setjmp.S | 103 csinc w0, w1, wzr, ne
|
| setjmp.S | 115 csinc w0, w1, wzr, ne
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm64.cc | [all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | 326 ### csinc ###
330 void csinc(const Register& rd,
|
| /art/compiler/dex/quick/arm64/ |
| fp_arm64.cc | 297 // csinc wD, wzr, wzr, eq
|
| int_arm64.cc | 46 * csinc wC, wzr, wzr, eq // wC = (xA == xB) ? 0 : 1
94 true_val == 1 || // Potentially Csinc.
96 true_val == false_val + 1) { // Potentially Csinc.
[all...] |
| arm64_lir.h | 255 kA64Csinc4rrrc, // csinc [s0011010100] rm[20-16] cond[15-12] [01] rn[9-5] rd[4-0].
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 45 CSINC, // Conditional select increment.
|
| AArch64InstrInfo.cpp | 324 // add x, 1 -> csinc.
387 // Single-cycle csel, csinc, csinv, and csneg.
519 // The folded opcodes csinc, csinc and csneg apply the operation to
[all...] |
| AArch64ISelLowering.cpp | 153 // to fold it into CSINC/CSINV.
343 // Also, try to fold ADD into CSINC/CSINV..
659 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
[all...] |
| AArch64SchedCyclone.td | 144 // CSEL,CSINC,CSINV,CSNEG
|
| /external/vixl/src/a64/ |
| assembler-a64.cc | 789 void Assembler::csinc(const Register& rd, function in class:vixl::Assembler
793 ConditionalSelect(rd, rn, rm, cond, CSINC);
816 csinc(rd, zr, zr, InvertCondition(cond));
829 csinc(rd, rn, rn, InvertCondition(cond));
[all...] |
| macro-assembler-a64.h | 479 void Csinc(const Register& rd,
488 csinc(rd, rn, rm, cond);
[all...] |
| constants-a64.h | 798 CSINC = CSINC_w,
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-arithmetic.txt | 516 # CHECK: csinc w1, w2, w3, eq
518 # CHECK: csinc x1, x2, x3, eq
|
| basic-a64-instructions.txt | 893 # CHECK: csinc w1, w0, w19, ne
894 # CHECK: csinc wzr, w5, w9, eq
895 # CHECK: csinc w9, wzr, w30, gt
896 # CHECK: csinc w1, w28, wzr, mi
897 # CHECK: csinc x19, x23, x29, lt
898 # CHECK: csinc xzr, x3, x4, ge
899 # CHECK: csinc x5, xzr, x6, hs
900 # CHECK: csinc x7, x8, xzr, lo
949 # CHECK: csinc w2, wzr, wzr, al
965 # CHECK: csinc w5, w6, w6, n
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeARM_64.c | 80 #define CSINC 0x9a800400
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 481 void MacroAssembler::Csinc(const Register& rd,
488 csinc(rd, rn, rm, cond);
[all...] |
| assembler-arm64.cc | 1336 void Assembler::csinc(const Register& rd, function in class:v8::internal::Assembler
[all...] |
| constants-arm64.h | [all...] |
| /external/llvm/test/MC/AArch64/ |
| arm64-arithmetic-encoding.s | 552 csinc w1, w2, w3, eq
553 csinc x1, x2, x3, eq
|
| basic-a64-instructions.s | [all...] |
