| /external/libhevc/common/arm64/ |
| ihevc_deblk_luma_horz.s | 137 csneg x9,x9,x9,pl
142 csneg x8,x8,x8,pl // dp0 value is stored in x8
166 csneg x12,x12,x12,pl
172 csneg x11,x11,x11,pl // dp3 value is stored in x8
228 csneg x2,x2,x2,pl
231 csneg x8,x8,x8,pl
240 csneg x7,x7,x7,pl
284 csneg x8,x8,x8,pl
288 csneg x2,x2,x2,pl
298 csneg x7,x7,x7,p
[all...] |
| ihevc_deblk_luma_vert.s | 130 csneg x9,x9,x9,pl
140 csneg x8,x8,x8,pl
165 csneg x12,x12,x12,pl
171 csneg x11,x11,x11,pl // dp3 value is stored in x8
226 csneg x8,x8,x8,pl
229 csneg x2,x2,x2,pl
239 csneg x7,x7,x7,pl
279 csneg x8,x8,x8,pl
283 csneg x2,x2,x2,pl
292 csneg x7,x7,x7,p
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-csel.ll | 83 ; CHECK-next: csneg
159 ; CHECK: csneg w0, w1, w2, ne
170 ; CHECK: csneg x0, x1, x2, ne
|
| arm64-early-ifcvt.ll | 186 ; CHECK-NEXT: csneg w0, w1, w0, eq
204 ; CHECK-NEXT: csneg x0, x1, x0, eq
222 ; CHECK-NEXT: csneg w0, w1, w0, ne
240 ; CHECK-NEXT: csneg x0, x1, x0, ne
|
| cond-sel.ll | 147 ; CHECK: csneg {{w[0-9]+}}, [[LHS]], [[RHS]], ls
155 ; CHECK: csneg {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
164 ; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
172 ; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm64.cc | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | 346 ### csneg ###
350 void csneg(const Register& rd,
|
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| /art/compiler/dex/quick/arm64/ |
| fp_arm64.cc | 298 // csneg wD, wD, wD, le
|
| arm64_lir.h | 257 kA64Csneg4rrrc, // csneg [s1011010100] rm[20-16] cond[15-12] [01] rn[9-5] rd[4-0].
|
| assemble_arm64.cc | 214 "csneg", "!0r, !1r, !2r, !3c", kFixupNone),
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 44 CSNEG, // Conditional select negate.
|
| AArch64SchedCyclone.td | 144 // CSEL,CSINC,CSINV,CSNEG
|
| AArch64InstrInfo.cpp | 351 // neg x -> csneg, represented as sub dst, xzr, src.
387 // Single-cycle csel, csinc, csinv, and csneg.
519 // The folded opcodes csinc, csinc and csneg apply the operation to
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-arithmetic.txt | 524 # CHECK: csneg w1, w2, w3, eq
526 # CHECK: csneg x1, x2, x3, eq
|
| basic-a64-instructions.txt | 927 # CHECK: csneg w1, w0, w19, ne
928 # CHECK: csneg wzr, w5, w9, eq
929 # CHECK: csneg w9, wzr, w30, gt
930 # CHECK: csneg w1, w28, wzr, mi
931 # CHECK: csneg x19, x23, x29, lt
932 # CHECK: csneg xzr, x3, x4, ge
933 # CHECK: csneg x5, xzr, x6, hs
934 # CHECK: csneg x7, x8, xzr, lo
1001 # CHECK: csneg x4, x8, x8, al
[all...] |
| /external/vixl/src/a64/ |
| assembler-a64.cc | 805 void Assembler::csneg(const Register& rd, function in class:vixl::Assembler
809 ConditionalSelect(rd, rn, rm, cond, CSNEG);
841 csneg(rd, rn, rn, InvertCondition(cond));
[all...] |
| macro-assembler-a64.h | 501 void Csneg(const Register& rd,
510 csneg(rd, rn, rm, cond);
[all...] |
| constants-a64.h | 804 CSNEG = CSNEG_w
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 503 void MacroAssembler::Csneg(const Register& rd,
510 csneg(rd, rn, rm, cond);
[all...] |
| constants-arm64.h | [all...] |
| assembler-arm64.cc | 1352 void Assembler::csneg(const Register& rd, function in class:v8::internal::Assembler
[all...] |
| disasm-arm64.cc | 410 mnemonic = "csneg";
[all...] |
| /external/llvm/test/MC/AArch64/ |
| arm64-arithmetic-encoding.s | 556 csneg w1, w2, w3, eq
557 csneg x1, x2, x3, eq
|
| basic-a64-instructions.s | [all...] |
