| /external/llvm/test/MC/AArch64/ |
| elf-reloc-ldrlit.s | 6 ldrsw x9, some_label
|
| arm64-elf-relocs.s | 170 ldrsw x3, [x4, #:lo12:sym]
173 // CHECK: ldrsw x3, [x4, :lo12:sym]
180 ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
183 // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
191 ldrsw x3, [x4, :tprel_lo12_nc:sym]
194 // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
|
| arm64-tls-relocs.s | 143 ldrsw x21, [x20, #:tprel_lo12_nc:var]
146 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
267 ldrsw x21, [x20, #:dtprel_lo12_nc:var]
270 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
|
| tls-relocs.s | 153 ldrsw x21, [x20, #:dtprel_lo12_nc:var]
157 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
355 ldrsw x21, [x20, #:tprel_lo12_nc:var]
359 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
|
| arm64-memory.s | 25 ldrsw x9, [sp, #512]
60 ; CHECK: ldrsw x9, [sp, #512] ; encoding: [0xe9,0x03,0x82,0xb9]
444 ldrsw x9, foo
449 ; CHECK: ldrsw x9, foo ; encoding: [0bAAA01001,A,A,0x98]
613 ldrsw x3, [x10, #10]
614 ldrsw x4, [x11, #-1]
|
| basic-a64-instructions.s | [all...] |
| basic-a64-diagnostics.s | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-extend.ll | 8 ; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
|
| jump-table.ll | 28 ; CHECK-PIC: ldrsw [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #2]
|
| aarch64-fix-cortex-a53-835769.ll | 163 ; CHECK: ldrsw
167 ; CHECK-NOWORKAROUND: ldrsw
183 ; CHECK: ldrsw
187 ; CHECK-NOWORKAROUND: ldrsw
202 ; CHECK: ldrsw
205 ; CHECK-NOWORKAROUND: ldrsw
|
| arm64-register-offset-addressing.ll | 95 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
|
| arm64-indexed-memory.ll | 299 ; CHECK: ldrsw x[[REG:[0-9]+]], [x0, #4]!
|
| ldst-unsignedimm.ll | 141 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
|
| ldst-regoffset.ll | 124 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
|
| /external/chromium_org/v8/src/ic/arm64/ |
| ic-arm64.cc | 107 __ Ldrsw(scratch1, UntagSmiFieldMemOperand(scratch2, kDetailsOffset));
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| deoptimizer-arm64.cc | 228 __ Ldrsw(x1, MemOperand(x4, Deoptimizer::output_count_offset()));
|
| codegen-arm64.cc | 166 __ Ldrsw(length, UntagSmiFieldMemOperand(elements,
274 __ Ldrsw(length, UntagSmiFieldMemOperand(elements,
|
| code-stubs-arm64.cc | [all...] |
| full-codegen-arm64.cc | [all...] |
| macro-assembler-arm64.cc | [all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm64.cc | [all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | 494 ### ldrsw ###
498 void ldrsw(const Register& rt, const MemOperand& src)
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-memory.txt | 28 # CHECK: ldrsw x0, [x1, x0, lsl #2]
35 # CHECK: ldrsw x9, [sp, #512]
544 # CHECK: ldrsw x0, [x1, x0, lsl #2]
|
| basic-a64-instructions.txt | [all...] |
