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  /external/valgrind/main/none/tests/mips64/
move_instructions.stdout.exp-BE 1 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0
3 mtc1, mov.s, mfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
5 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0
7 mtc1, mov.s, mfc1 :: mem: 0x7e876382d2ab13 out: 0xffffffff82d2ab13
9 mtc1, mov.s, mfc1 :: mem: 0x9823b6e out: 0x9823b6e
11 mtc1, mov.s, mfc1 :: mem: 0x976d6e9ac31510f3 out: 0xffffffffc31510f3
13 mtc1, mov.s, mfc1 :: mem: 0xd4326d9 out: 0xd4326d9
15 mtc1, mov.s, mfc1 :: mem: 0xb7746d775ad6a5fb out: 0x5ad6a5fb
17 mtc1, mov.s, mfc1 :: mem: 0x130476dc out: 0x130476dc
19 mtc1, mov.s, mfc1 :: mem: 0x42b0c0a28677b502 out: 0xffffffff8677b50
    [all...]
move_instructions.stdout.exp-LE 1 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0
3 mtc1, mov.s, mfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
5 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0
7 mtc1, mov.s, mfc1 :: mem: 0x7e876382d2ab13 out: 0xffffffff82d2ab13
9 mtc1, mov.s, mfc1 :: mem: 0x9823b6e out: 0x9823b6e
11 mtc1, mov.s, mfc1 :: mem: 0x976d6e9ac31510f3 out: 0xffffffffc31510f3
13 mtc1, mov.s, mfc1 :: mem: 0xd4326d9 out: 0xd4326d9
15 mtc1, mov.s, mfc1 :: mem: 0xb7746d775ad6a5fb out: 0x5ad6a5fb
17 mtc1, mov.s, mfc1 :: mem: 0x130476dc out: 0x130476dc
19 mtc1, mov.s, mfc1 :: mem: 0x42b0c0a28677b502 out: 0xffffffff8677b50
    [all...]
macro_load_store.h 74 "mfc1 %0, $f0" "\n\t" \
129 "mfc1 %0, $f0" "\n\t" \
macro_fpu.h 95 "mfc1 %1, $f0" "\n\t" \
106 "mfc1 %1, $f0" "\n\t" \
  /external/llvm/test/CodeGen/Mips/
2008-08-04-Bitconvert.ll 12 ; CHECK: mfc1
buildpairextractelementf64.ll 22 ; FP32: mfc1
23 ; FP32: mfc1
24 ; FP64-DAG: mfc1
hf16call32_body.ll 24 ; stel: mfc1 $4,$f12
44 ; stel: mfc1 $4,$f12
45 ; stel: mfc1 $5,$f13
67 ; stel: mfc1 $4,$f12
68 ; stel: mfc1 $5,$f14
90 ; stel: mfc1 $4,$f12
91 ; stel: mfc1 $6,$f14
92 ; stel: mfc1 $7,$f15
114 ; stel: mfc1 $4,$f12
115 ; stel: mfc1 $5,$f1
    [all...]
hf1_body.ll 19 ; picfp16: mfc1 $4,$f12
o32_cc.ll 142 ; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
143 ; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}}
145 ; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
159 ; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
160 ; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}}
162 ; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
219 ; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}}
220 ; FP32EL-DAG: mfc1 $7, $f{{[0-9]+}}
222 ; FP64EL-DAG: mfc1 $6, $f{{[0-9]+}}
281 ; FP32EL-DAG: mfc1 $6, $f{{[0-9]+}
    [all...]
fcmp.ll 32 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
36 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
58 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
62 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
84 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
88 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
110 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
114 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
136 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
140 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]
    [all...]
mno-ldc1-sdc1.ll 120 ; 32R1-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
121 ; 32R1-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
125 ; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
126 ; 32R2-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
130 ; 32R6-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
135 ; 32R1-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
136 ; 32R1-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
142 ; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
143 ; 32R2-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
149 ; 32R6-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f1
    [all...]
fpbr.ll 18 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
52 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
81 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
110 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
140 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
169 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
hf16call32.ll     [all...]
analyzebranch.ll 20 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
51 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
select.ll 518 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
533 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
563 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
578 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
607 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
622 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
664 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
697 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
741 ; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
774 ; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]
    [all...]
  /external/valgrind/main/none/tests/mips32/
MoveIns.c 24 // mfc1 rt, fs
110 "mfc1 %1, $" #FD"\n\t" \
129 "mfc1 %1, $" #FD"\n\t" \
200 "mfc1 %1, $f4\n\t" \
226 "mfc1 %1, $f4\n\t" \
227 "mfc1 %2, $f5\n\t" \
249 "mfc1 %1, $" #FD"\n\t" \
271 "mfc1 %1, $" #FD"\n\t" \
282 printf("MFC1\n");
283 TESTINSNMOVE("mfc1 $t1, $f0", 0, f0, t1)
    [all...]
MoveIns.stdout.exp 0 MFC1
2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
10 mfc1 $v1, $f8 :: fs nan, rt 0xfffffff
    [all...]
MoveIns.stdout.exp-BE 0 MFC1
2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
10 mfc1 $v1, $f8 :: fs nan, rt 0xfffffff
    [all...]
vfp.c 59 "mfc1 %1, $" #RT "\n\t" \
79 "mfc1 %1, $" #RT "\n\t" \
80 "mfc1 %2, $f1\n\t" \
100 "mfc1 %1, $" #RT "\n\t" \
117 "mfc1 %0, $" #fd "\n\t" \
136 "mfc1 %0, $" #fd "\n\t" \
154 "mfc1 %0, $" #fd "\n\t" \
155 "mfc1 %1, $f1\n\t" \
round.c 98 "mfc1 %1, $f0" "\n\t" \
107 "mfc1 %1, $f0" "\n\t" \
  /external/llvm/lib/Target/Mips/
Mips16HardFloat.cpp 190 std::string MI = ToFP? "mtc1 ": "mfc1 ";
287 IAH.Out("mfc1 $$2,$$f0");
291 IAH.Out("mfc1 $$2,$$f0");
292 IAH.Out("mfc1 $$3,$$f1");
294 IAH.Out("mfc1 $$3,$$f0");
295 IAH.Out("mfc1 $$2,$$f1");
300 IAH.Out("mfc1 $$2,$$f0");
301 IAH.Out("mfc1 $$3,$$f2");
303 IAH.Out("mfc1 $$3,$$f0");
304 IAH.Out("mfc1 $$3,$$f2")
    [all...]
MicroMipsInstrFPU.td 122 def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
  /frameworks/native/opengl/libagl/arch-mips/
fixed_asm.S 32 mfc1 $a0,$f12
  /external/chromium_org/v8/test/cctest/
test-assembler-mips.cc 355 __ mfc1(t0, f4);
356 __ mfc1(t1, f5);
357 __ mfc1(t2, f6);
358 __ mfc1(t3, f7);
366 __ mfc1(t0, f4);
368 __ mfc1(t2, f6);
425 __ mfc1(t2, f8);
430 __ mfc1(t3, f10);
783 __ mfc1(t0, f0);
784 __ mfc1(t1, f1)
    [all...]
  /external/llvm/test/CodeGen/Mips/msa/
basic_operations.ll 418 ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
442 ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
465 ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
488 ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
490 ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
514 ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
538 ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
561 ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
584 ; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
586 ; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]
    [all...]

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