| /external/chromium_org/v8/src/arm64/ |
| assembler-arm64-inl.h | 468 Register regoffset,
471 : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
474 DCHECK(!regoffset.IsSP());
478 DCHECK(regoffset.Is64Bits() || (extend != SXTX));
483 Register regoffset,
486 : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
489 DCHECK(regoffset.Is64Bits() && !regoffset.IsSP());
558 return Operand(regoffset(), shift(), shift_amount());
560 return Operand(regoffset(), extend(), shift_amount())
[all...] |
| assembler-arm64.h | 705 Register regoffset,
709 Register regoffset,
717 const Register& regoffset() const { return regoffset_; }
[all...] |
| assembler-arm64.cc | [all...] |
| /external/llvm/docs/ |
| MarkedUpDisassembly.rst | 75 ldr <reg gpr:r0>, <mem regoffset:[<reg gpr:sp>, <imm:#4>]>
|
| /external/vixl/src/a64/ |
| assembler-a64.cc | 278 Register regoffset,
281 : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
284 VIXL_ASSERT(!regoffset.IsSP());
288 VIXL_ASSERT(regoffset.Is64Bits() || (extend != SXTX));
293 Register regoffset,
296 : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
299 VIXL_ASSERT(regoffset.Is64Bits() && !regoffset.IsSP());
[all...] |
| assembler-a64.h | 541 Register regoffset,
545 Register regoffset,
553 const Register& regoffset() const { return regoffset_; }
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| TargetInfo.cpp | [all...] |
