| /external/llvm/test/TableGen/ |
| Tree.td | 6 class RegisterClass;
11 def R32 : RegisterClass;
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| TreeNames.td | 6 class RegisterClass;
11 def R32 : RegisterClass;
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| MultiPat.td | 45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
67 def VR128 : RegisterClass<[v2i64, v2f64],
73 def REGCLASS : RegisterClass<[], []>;
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| TargetInstrSpec.td | 42 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
64 def VR128 : RegisterClass<[v2i64, v2f64],
70 def REGCLASS : RegisterClass<[], []>;
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| cast.td | 41 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
63 def VR128 : RegisterClass<[v2i64, v2f64],
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| TargetInstrInfo.td | 11 class RegisterClass;
35 def R8 : RegisterClass;
36 def R16 : RegisterClass;
37 def R32 : RegisterClass;
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| /external/llvm/lib/Target/R600/ |
| R600RegisterInfo.td | 151 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
161 def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;
166 def R600_Addr_Y : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Y)>;
167 def R600_Addr_Z : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Z)>;
168 def R600_Addr_W : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_W)>;
170 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
173 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
176 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
179 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
182 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32
[all...] |
| SIRegisterInfo.td | 51 def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
98 def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
155 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
156 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
157 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
158 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
161 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
165 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;
167 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
171 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)>
[all...] |
| SIInstrInfo.td | 218 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
239 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
240 RegisterClass dstClass> {
289 multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
320 multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
348 RegisterClass src0_rc, string revOp = opName> {
371 multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.td | 318 def GR8 : RegisterClass<"X86", [i8], 8,
327 def GR16 : RegisterClass<"X86", [i16], 16,
331 def GR32 : RegisterClass<"X86", [i32], 32,
338 def GR64 : RegisterClass<"X86", [i64], 64,
345 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
348 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>;
351 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
359 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
360 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
361 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUInstructions.td | 96 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
103 class FABS <RegisterClass rc> : AMDGPUShaderInst <
110 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
123 RegisterClass rc> : Pat <
133 RegisterClass vec_class, int sub_idx,
141 RegisterClass elem_class, RegisterClass vec_class,
150 class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat <
156 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
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| R600GenRegisterInfo.pl | 77 def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
80 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
83 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add
86 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
91 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
94 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
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| SIInstrFormats.td | 47 class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
70 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
100 class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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| SIGenRegisterInfo.pl | 142 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
146 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
167 def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
171 def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
173 def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
195 def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64,
285 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstructions.td | 96 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
103 class FABS <RegisterClass rc> : AMDGPUShaderInst <
110 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
123 RegisterClass rc> : Pat <
133 RegisterClass vec_class, int sub_idx,
141 RegisterClass elem_class, RegisterClass vec_class,
150 class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat <
156 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
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| R600GenRegisterInfo.pl | 77 def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
80 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
83 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add
86 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
91 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
94 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
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| SIInstrFormats.td | 47 class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
70 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
100 class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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| SIGenRegisterInfo.pl | 142 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
146 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
167 def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
171 def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
173 def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
195 def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64,
285 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";
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| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.td | 269 RegisterClass<"Mips", regTypes, 32, (add
286 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
300 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
306 def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
313 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
315 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
324 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
326 def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
329 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
341 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>
[all...] |
| MipsCondMov.td | 55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
80 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
88 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
95 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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| /external/clang/test/SemaObjC/ |
| super-dealloc-attribute.m | 23 + (void)registerClass:(id)name __attribute((objc_requires_super));
47 + (void)registerClass:(id)name {} // expected-warning {{method possibly missing a [super registerClass:] call}}
83 + (void)registerClass:(id)name {
84 [super registerClass:name]; // no-warning
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 228 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
232 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
239 def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>;
240 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>;
249 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
251 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
253 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
260 def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
263 def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
269 def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 193 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
209 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
219 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
231 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>;
237 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
246 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
249 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
255 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
263 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
272 def SPR : RegisterClass<"ARM", [f32], 32, (add (decimat
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 126 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {
130 def GPR64common : RegisterClass<"AArch64", [i64], 64,
136 def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {
140 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
146 def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> {
150 def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> {
155 def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>;
156 def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>;
170 def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)>;
171 def GPR64all : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR, SP)>
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.td | 191 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
201 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
204 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
206 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
208 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
211 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
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