| /external/llvm/test/CodeGen/Mips/ |
| bswap.ll | 9 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
13 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
36 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
38 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
76 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
78 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
80 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
82 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
86 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
88 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 1
[all...] |
| rotate.ll | 15 ; CHECK: rotr $2, $4, 22
36 ; CHECK: rotr $2, $4, 10
|
| /external/wpa_supplicant_8/src/crypto/ |
| aes_i.h | 70 static inline u32 rotr(u32 val, int bits) function
76 #define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)
77 #define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)
78 #define TE3(i) rotr(Te0[(i) & 0xff], 24)
94 #define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)
95 #define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)
96 #define TD3(i) rotr(Td0[(i) & 0xff], 24)
102 #define TD1_(i) rotr(Td0[(i) & 0xff], 8)
103 #define TD2_(i) rotr(Td0[(i) & 0xff], 16)
104 #define TD3_(i) rotr(Td0[(i) & 0xff], 24
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-regress-interphase-shift.ll | 5 ; unselectable "rotr" node: (i32 (rotr i32, i64)).
|
| /external/llvm/test/TableGen/ |
| SetTheory.td | 115 // The 'rotr' operator rotates right, but also accepts a negative shift.
116 def rotr;
117 def S7a : Set<(rotr S0f, 0)>;
118 def S7b : Set<(rotr S0f, 1)>;
119 def S7c : Set<(rotr S0f, 3)>;
120 def S7d : Set<(rotr S0f, 4)>;
121 def S7e : Set<(rotr S0f, 5)>;
122 def S7f : Set<(rotr S0f, -1)>;
123 def S7g : Set<(rotr S0f, -4)>;
124 def S7h : Set<(rotr S0f, -5)>
[all...] |
| /ndk/tests/build/issue17144-byteswap/ |
| build.sh | 50 grep -w rotr issue17144-byteswap.s | grep -qw rotr
51 fail_panic "mips doesn't use wsbh/rotr instruciton for __swap32()"
|
| /external/openssl/crypto/des/asm/ |
| crypt586.pl | 109 &rotr( $t, 4 );
174 { &rotr($tt, 3-$lr); }
180 { &rotr($r, 2-$lr); }
193 else { &rotr($r, $lr-2); }
199 else { &rotr($l, $lr-3); }
207 &rotr($tt , 4);
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 29 case ISD::ROTR: return ARM_AM::ror;
30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
|
| /development/ndk/sources/android/libportable/arch-mips/ |
| md_swap.c | 33 __asm volatile ("wsbh %0, %1; rotr %0, %0, 16" : "=r" (_r) : "r" (_x));
|
| /external/chromium_org/third_party/boringssl/src/crypto/sha/ |
| sha512.c | 344 #define ROTR(a, n) \
365 #define ROTR(a, n) \
372 #define ROTR(a, n) \
391 #define ROTR(a, n) _rotr64((a), n)
415 #ifndef ROTR
416 #define ROTR(x, s) (((x) >> s) | (x) << (64 - s))
419 #define Sigma0(x) (ROTR((x), 28) ^ ROTR((x), 34) ^ ROTR((x), 39))
420 #define Sigma1(x) (ROTR((x), 14) ^ ROTR((x), 18) ^ ROTR((x), 41)
[all...] |
| /external/kernel-headers/original/uapi/asm-mips/asm/ |
| swab.h | 33 " rotr %0, %0, 16 \n"
|
| /external/valgrind/main/none/tests/mips64/ |
| shift_instructions.c | 9 ROTR, ROTRV, SLL, SLLV,
143 case ROTR:
146 TEST2("rotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
147 TEST2("rotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
148 TEST2("rotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
149 TEST2("rotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
|
| /external/llvm/unittests/ADT/ |
| APIntTest.cpp | 158 EXPECT_EQ(one, one.rotr(0));
159 EXPECT_EQ(one, one.rotr(1));
508 EXPECT_EQ(APInt(8, 16), APInt(8, 16).rotr(0));
509 EXPECT_EQ(APInt(8, 8), APInt(8, 16).rotr(1));
510 EXPECT_EQ(APInt(8, 4), APInt(8, 16).rotr(2));
511 EXPECT_EQ(APInt(8, 1), APInt(8, 16).rotr(4));
512 EXPECT_EQ(APInt(8, 16), APInt(8, 16).rotr(8));
514 EXPECT_EQ(APInt(8, 1), APInt(8, 1).rotr(0));
515 EXPECT_EQ(APInt(8, 128), APInt(8, 1).rotr(1));
516 EXPECT_EQ(APInt(8, 64), APInt(8, 1).rotr(2))
[all...] |
| /external/chromium_org/third_party/skia/bench/ |
| FontCacheBench.cpp | 57 static uint32_t rotr(uint32_t value, unsigned bits) { function
104 if (false) rotr(0, 0);
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips.cc | 356 COMPARE(rotr(a0, a1, 0),
357 "00252002 rotr a0, a1, 0");
358 COMPARE(rotr(s0, s1, 8),
359 "00318202 rotr s0, s1, 8");
360 COMPARE(rotr(t2, t3, 24),
361 "002b5602 rotr t2, t3, 24");
362 COMPARE(rotr(v0, v1, 31),
363 "002317c2 rotr v0, v1, 31");
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 24 rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/openssl/crypto/bf/asm/ |
| bf-686.pl | 95 &rotr( $R, 16);
101 &rotr( $R, 16);
|
| /external/skia/bench/ |
| FontCacheBench.cpp | 56 static uint32_t rotr(uint32_t value, unsigned bits) { function
114 if (false) rotr(0, 0);
|
| /external/chromium_org/third_party/skia/src/core/ |
| SkChecksum.h | 29 ROTR = 17,
30 ROTL = sizeof(uintptr_t) * 8 - ROTR,
35 return ((total >> ROTR) | (total << ROTL)) ^ value;
|
| /external/llvm/test/MC/Mips/ |
| micromips-shift-instructions.s | 16 # CHECK-EL: rotr $9, $6, 7 # encoding: [0x26,0x01,0xc0,0x38]
27 # CHECK-EB: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
35 rotr $9, $6, 7
|
| /external/skia/include/core/ |
| SkChecksum.h | 29 ROTR = 17,
30 ROTL = sizeof(uintptr_t) * 8 - ROTR,
35 return ((total >> ROTR) | (total << ROTL)) ^ value;
|
| /external/openssl/crypto/sha/ |
| sha512.c | 316 # define ROTR(a,n) ({ SHA_LONG64 ret; \
346 # define ROTR(a,n) ({ SHA_LONG64 ret; \
354 # define ROTR(a,n) _rotr64((a),n)
389 #ifndef ROTR
390 #define ROTR(x,s) (((x)>>s) | (x)<<(64-s))
393 #define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
394 #define Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)
[all...] |
| /external/openssl/crypto/sha/asm/ |
| sha512-ia64.pl | 182 .rotr X[16]
220 _rotr r11=$t1,$Sigma1[0] } // ROTR(e,14)
453 _rotr r11=$t1,$Sigma1[0] } // ROTR(e,14)
459 _rotr r8=$t1,$Sigma1[1] } // ROTR(e,18)
463 _rotr r9=$t1,$Sigma1[2] } // ROTR(e,41)
467 _rotr r10=$t0,$Sigma0[0] } // ROTR(a,28)
471 _rotr r11=$t0,$Sigma0[1] } // ROTR(a,34)
475 _rotr r8=$t0,$Sigma0[2] } // ROTR(a,39)
491 .rotr X[16]
493 _rotr r8=X[15-1],$sigma0[0] } // ROTR(s0,1
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrShiftRotate.td | 580 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
583 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
586 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
589 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
594 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
597 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
601 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
606 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
612 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
616 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]
[all...] |
| /bionic/libc/arch-mips/include/machine/ |
| endian.h | 45 __asm volatile ("wsbh %0, %1; rotr %0, %0, 16" : "=r" (_r) : "r" (_x)); \
|
