Lines Matching refs:ArmMir2Lir
28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
43 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) {
71 void ArmMir2Lir::UpdateIT(LIR* it, const char* new_guide) {
99 void ArmMir2Lir::OpEndIT(LIR* it) {
122 void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
155 void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
206 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
230 void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
305 void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
367 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) {
401 LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
428 void ArmMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) {
435 void ArmMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) {
492 bool ArmMir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div,
552 bool ArmMir2Lir::GetEasyMultiplyOp(int lit, ArmMir2Lir::EasyMultiplyOp* op) {
585 bool ArmMir2Lir::GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops) {
623 void ArmMir2Lir::GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops) {
669 bool ArmMir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) {
684 RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
690 RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) {
695 RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) {
709 RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2,
731 bool ArmMir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) {
751 bool ArmMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) {
776 bool ArmMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) {
796 bool ArmMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) {
960 bool ArmMir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) {
1055 LIR* ArmMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) {
1059 LIR* ArmMir2Lir::OpVldm(RegStorage r_base, int count) {
1063 LIR* ArmMir2Lir::OpVstm(RegStorage r_base, int count) {
1067 void ArmMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
1077 void ArmMir2Lir::GenDivZeroCheckWide(RegStorage reg) {
1086 LIR* ArmMir2Lir::OpTestSuspend(LIR* target) {
1102 LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) {
1109 bool ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
1145 void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {
1165 void ArmMir2Lir::GenMulLong(Instruction::Code opcode, RegLocation rl_dest,
1271 void ArmMir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
1293 void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
1381 void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
1471 void ArmMir2Lir::GenShiftImmOpLong(Instruction::Code opcode,
1544 void ArmMir2Lir::GenArithImmOpLong(Instruction::Code opcode,
