Lines Matching refs:ArmMir2Lir
72 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) {
120 int ArmMir2Lir::ModifiedImmediate(uint32_t value) {
149 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) {
153 bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) {
157 bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) {
161 bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) {
173 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
207 LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) {
213 LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
223 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
238 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
371 LIR* ArmMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
375 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
380 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
390 LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1,
459 LIR* ArmMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) {
463 LIR* ArmMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) {
600 LIR* ArmMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
641 LIR* ArmMir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) {
688 int ArmMir2Lir::EncodeShift(int code, int amount) {
692 LIR* ArmMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
758 LIR* ArmMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
824 LIR* ArmMir2Lir::LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base,
854 LIR* ArmMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
965 LIR* ArmMir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
995 LIR* ArmMir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
1087 LIR* ArmMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
1141 LIR* ArmMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
1161 LIR* ArmMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) {
1166 LIR* ArmMir2Lir::InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) {
1170 size_t ArmMir2Lir::GetInstructionOffset(LIR* lir) {
