Lines Matching refs:s_reg_low
45 int pmap_index = SRegToPMap(rl_dest.s_reg_low);
49 int base_vreg = mir_graph_->SRegToVReg(rl_dest.s_reg_low);
51 if (mir_graph_->SRegToVReg(mir_graph_->reg_location_[i].s_reg_low) == base_vreg) {
69 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), temp_reg, k32, kNotVolatile);
96 LoadRefDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, kNotVolatile);
98 Load32Disp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest);
129 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, k64, kNotVolatile);
161 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG);
181 (rl_dest.s_reg_low != live_sreg_));
182 live_sreg_ = rl_dest.s_reg_low;
214 if (IsDirty(rl_dest.reg) && LiveOut(rl_dest.s_reg_low)) {
218 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, kNotVolatile);
220 Store32Disp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg);
248 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG);
249 DCHECK_NE(GetSRegHi(rl_src.s_reg_low), INVALID_SREG);
265 (rl_dest.s_reg_low != live_sreg_));
266 live_sreg_ = rl_dest.s_reg_low;
302 if (IsDirty(rl_dest.reg) && (LiveOut(rl_dest.s_reg_low) ||
303 LiveOut(GetSRegHi(rl_dest.s_reg_low)))) {
305 DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1),
306 mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low)));
308 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64, kNotVolatile);
333 if (IsDirty(rl_dest.reg) && LiveOut(rl_dest.s_reg_low)) {
336 Store32Disp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg);
366 if (IsDirty(rl_dest.reg) && (LiveOut(rl_dest.s_reg_low) ||
367 LiveOut(GetSRegHi(rl_dest.s_reg_low)))) {
369 DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1),
370 mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low)));
372 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64, kNotVolatile);
401 loc.s_reg_low = INVALID_SREG;
436 loc.s_reg_low = INVALID_SREG;
