Lines Matching refs:MIR
1685 void X86Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) {
1686 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
1688 ReserveVectorRegisters(mir);
1694 GenConst128(bb, mir);
1697 GenMoveVector(bb, mir);
1700 GenMultiplyVector(bb, mir);
1703 GenAddVector(bb, mir);
1706 GenSubtractVector(bb, mir);
1709 GenShiftLeftVector(bb, mir);
1712 GenSignedShiftRightVector(bb, mir);
1715 GenUnsignedShiftRightVector(bb, mir);
1718 GenAndVector(bb, mir);
1721 GenOrVector(bb, mir);
1724 GenXorVector(bb, mir);
1727 GenAddReduceVector(bb, mir);
1730 GenReduceVector(bb, mir);
1733 GenSetVector(bb, mir);
1740 void X86Mir2Lir::ReserveVectorRegisters(MIR* mir) {
1744 int num_vector_reg = mir->dalvikInsn.vA;
1785 void X86Mir2Lir::GenConst128(BasicBlock* bb, MIR* mir) {
1787 int type_size = mir->dalvikInsn.vB;
1790 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);
1791 uint32_t *args = mir->dalvikInsn.arg;
1800 AppendOpcodeWithConst(kX86MovupsRM, reg, mir);
1803 void X86Mir2Lir::AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) {
1805 LIR *data_target = ScanVectorLiteral(mir);
1807 data_target = AddVectorLiteral(mir);
1828 void X86Mir2Lir::GenMoveVector(BasicBlock *bb, MIR *mir) {
1830 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1831 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);
1832 RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB);
1836 void X86Mir2Lir::GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir) {
1838 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1839 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
1878 void X86Mir2Lir::GenMultiplyVector(BasicBlock *bb, MIR *mir) {
1879 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1880 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1881 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1882 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
1899 GenMultiplyVectorSignedByte(bb, mir);
1908 void X86Mir2Lir::GenAddVector(BasicBlock *bb, MIR *mir) {
1909 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1910 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1911 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1912 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
1939 void X86Mir2Lir::GenSubtractVector(BasicBlock *bb, MIR *mir) {
1940 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
1941 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
1942 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1943 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
1970 void X86Mir2Lir::GenShiftByteVector(BasicBlock *bb, MIR *mir) {
1971 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
1975 int imm = mir->dalvikInsn.vB;
1977 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
2019 void X86Mir2Lir::GenShiftLeftVector(BasicBlock *bb, MIR *mir) {
2020 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2021 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2022 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2023 int imm = mir->dalvikInsn.vB;
2038 GenShiftByteVector(bb, mir);
2047 void X86Mir2Lir::GenSignedShiftRightVector(BasicBlock *bb, MIR *mir) {
2048 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2049 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2050 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2051 int imm = mir->dalvikInsn.vB;
2063 GenShiftByteVector(bb, mir);
2072 void X86Mir2Lir::GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir) {
2073 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2074 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2075 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2076 int imm = mir->dalvikInsn.vB;
2091 GenShiftByteVector(bb, mir);
2100 void X86Mir2Lir::GenAndVector(BasicBlock *bb, MIR *mir) {
2102 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2103 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2104 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
2108 void X86Mir2Lir::GenOrVector(BasicBlock *bb, MIR *mir) {
2110 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2111 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2112 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
2116 void X86Mir2Lir::GenXorVector(BasicBlock *bb, MIR *mir) {
2118 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2119 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);
2120 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);
2129 // Create temporary MIR as container for 128-bit binary mask.
2130 MIR const_mir;
2131 MIR* const_mirp = &const_mir;
2142 void X86Mir2Lir::GenAddReduceVector(BasicBlock *bb, MIR *mir) {
2143 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2144 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB);
2145 RegLocation rl_dest = mir_graph_->GetDest(mir);
2148 int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8;
2235 void X86Mir2Lir::GenReduceVector(BasicBlock *bb, MIR *mir) {
2236 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2237 RegLocation rl_dest = mir_graph_->GetDest(mir);
2238 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB);
2239 int extract_index = mir->dalvikInsn.arg[0];
2275 void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) {
2276 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);
2277 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);
2278 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);
2317 RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
2348 LIR *X86Mir2Lir::ScanVectorLiteral(MIR *mir) {
2349 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg);
2359 LIR *X86Mir2Lir::AddVectorLiteral(MIR *mir) {
2361 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg);
