Lines Matching defs:rn
28 void Thumb2Assembler::and_(Register rd, Register rn, const ShifterOperand& so,
30 EmitDataProcessing(cond, AND, 0, rn, rd, so);
34 void Thumb2Assembler::eor(Register rd, Register rn, const ShifterOperand& so,
36 EmitDataProcessing(cond, EOR, 0, rn, rd, so);
40 void Thumb2Assembler::sub(Register rd, Register rn, const ShifterOperand& so,
42 EmitDataProcessing(cond, SUB, 0, rn, rd, so);
46 void Thumb2Assembler::rsb(Register rd, Register rn, const ShifterOperand& so,
48 EmitDataProcessing(cond, RSB, 0, rn, rd, so);
52 void Thumb2Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so,
54 EmitDataProcessing(cond, RSB, 1, rn, rd, so);
58 void Thumb2Assembler::add(Register rd, Register rn, const ShifterOperand& so,
60 EmitDataProcessing(cond, ADD, 0, rn, rd, so);
64 void Thumb2Assembler::adds(Register rd, Register rn, const ShifterOperand& so,
66 EmitDataProcessing(cond, ADD, 1, rn, rd, so);
70 void Thumb2Assembler::subs(Register rd, Register rn, const ShifterOperand& so,
72 EmitDataProcessing(cond, SUB, 1, rn, rd, so);
76 void Thumb2Assembler::adc(Register rd, Register rn, const ShifterOperand& so,
78 EmitDataProcessing(cond, ADC, 0, rn, rd, so);
82 void Thumb2Assembler::sbc(Register rd, Register rn, const ShifterOperand& so,
84 EmitDataProcessing(cond, SBC, 0, rn, rd, so);
88 void Thumb2Assembler::rsc(Register rd, Register rn, const ShifterOperand& so,
90 EmitDataProcessing(cond, RSC, 0, rn, rd, so);
94 void Thumb2Assembler::tst(Register rn, const ShifterOperand& so, Condition cond) {
95 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker.
96 EmitDataProcessing(cond, TST, 1, rn, R0, so);
100 void Thumb2Assembler::teq(Register rn, const ShifterOperand& so, Condition cond) {
101 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker.
102 EmitDataProcessing(cond, TEQ, 1, rn, R0, so);
106 void Thumb2Assembler::cmp(Register rn, const ShifterOperand& so, Condition cond) {
107 EmitDataProcessing(cond, CMP, 1, rn, R0, so);
111 void Thumb2Assembler::cmn(Register rn, const ShifterOperand& so, Condition cond) {
112 EmitDataProcessing(cond, CMN, 1, rn, R0, so);
116 void Thumb2Assembler::orr(Register rd, Register rn,
118 EmitDataProcessing(cond, ORR, 0, rn, rd, so);
122 void Thumb2Assembler::orrs(Register rd, Register rn,
124 EmitDataProcessing(cond, ORR, 1, rn, rd, so);
138 void Thumb2Assembler::bic(Register rd, Register rn, const ShifterOperand& so,
140 EmitDataProcessing(cond, BIC, 0, rn, rd, so);
154 void Thumb2Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
155 if (rd == rm && !IsHighRegister(rd) && !IsHighRegister(rn) && !force_32bit_) {
158 rn << 3 | rd;
169 static_cast<uint32_t>(rn) << 16 |
177 void Thumb2Assembler::mla(Register rd, Register rn, Register rm, Register ra,
186 static_cast<uint32_t>(rn) << 16 |
193 void Thumb2Assembler::mls(Register rd, Register rn, Register rm, Register ra,
202 static_cast<uint32_t>(rn) << 16 |
209 void Thumb2Assembler::umull(Register rd_lo, Register rd_hi, Register rn,
218 static_cast<uint32_t>(rn) << 16 |
225 void Thumb2Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
233 static_cast<uint32_t>(rn) << 16 |
240 void Thumb2Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
248 static_cast<uint32_t>(rn) << 16 |
615 Register rn,
623 || ((opcode == ADD || opcode == SUB) && (rn == rd));
625 if (IsHighRegister(rd) || IsHighRegister(rn)) {
635 // If rn is SP and rd is a high register we need to use a 32 bit encoding.
636 if (rn == SP && rd != SP && IsHighRegister(rd)) {
642 if (rd == SP && rn == SP) {
646 } else if (opcode == ADD && rd != SP && rn == SP) { // 10 bit immediate.
650 } else if (opcode == SUB && rd != SP && rn == SP) {
687 rn_is_valid = false; // There is no Rn for these instructions.
696 if (so.IsRegister() && rd != rn) {
702 if (rn_is_valid && rn != rd) {
733 Register rn,
751 case MOV: thumb_opcode = 0b0010; rn = PC; break;
753 case MVN: thumb_opcode = 0b0011; rn = PC; break;
779 rn << 16 |
793 rn << 16 |
802 rn << 16 |
813 Register rn,
817 Emit16BitAddSub(cond, opcode, set_cc, rn, rd, so);
839 rn = so.GetRegister();
871 case TST: thumb_opcode = 0b1000; rn = so.GetRegister(); break;
883 rd = rn;
884 rn = so.GetRegister();
890 rd = rn;
891 rn = so.GetRegister();
904 rn = so.GetRegister();
905 if (IsHighRegister(rn) || IsHighRegister(rd)) {
918 case MVN: thumb_opcode = 0b1111; rn = so.GetRegister(); break;
931 rn << rn_shift |
942 Register rn,
963 if (rn == rd) {
968 // Make Rn also contain the top bit of rd.
969 rn = static_cast<Register>(static_cast<uint32_t>(rm) |
982 if (rd == SP && rn == SP) {
990 // Remove rd and rn from instruction by orring it with immed and clearing bits.
991 rn = R0;
996 } else if (rd != SP && rn == SP) {
1004 // Remove rn from instruction.
1005 rn = R0;
1009 } else if (rn != rd) {
1033 if (rd == SP && rn == SP) {
1041 // Remove rd and rn from instruction by orring it with immed and clearing bits.
1042 rn = R0;
1047 } else if (rn != rd) {
1069 rn << rn_shift |
1079 Register rn,
1085 if (Is32BitDataProcessing(cond, opcode, set_cc, rn, rd, so)) {
1086 Emit32BitDataProcessing(cond, opcode, set_cc, rn, rd, so);
1088 Emit16BitDataProcessing(cond, opcode, set_cc, rn, rd, so);
1129 void Thumb2Assembler::EmitShift(Register rd, Register rn, Shift shift, Register rm, bool setcc) {
1132 if (IsHighRegister(rd) || IsHighRegister(rm) || IsHighRegister(rn) || rd != rn) {
1149 encoding |= static_cast<int16_t>(rn) << 16 | static_cast<int16_t>(rm) |
1232 uint16_t Thumb2Assembler::EmitCompareAndBranch(Register rn, uint16_t prev, bool n) {
1238 location, rn);
1258 Register rn = ad.GetRegister();
1259 if (IsHighRegister(rn) && rn != SP && rn != PC) {
1272 if (rn == SP && offset >= (1 << 10)) {
1311 if (rn == SP) {
1346 encoding |= rn << 3 | offset << 6;
1575 void Thumb2Assembler::ldrex(Register rt, Register rn, uint16_t imm, Condition cond) {
1576 CHECK_NE(rn, kNoRegister);
1579 CHECK_NE(rn, kNoRegister);
1585 static_cast<uint32_t>(rn) << 16 |
1593 void Thumb2Assembler::ldrex(Register rt, Register rn, Condition cond) {
1594 ldrex(rt, rn, 0, cond);
1600 Register rn,
1603 CHECK_NE(rn, kNoRegister);
1610 static_cast<uint32_t>(rn) << 16 |
1620 Register rn,
1622 strex(rd, rt, rn, 0, cond);
2011 void Thumb2Assembler::cbz(Register rn, Label* label) {
2016 uint16_t branchid = EmitCompareAndBranch(rn, static_cast<uint16_t>(label->position_), false);
2022 void Thumb2Assembler::cbnz(Register rn, Label* label) {
2027 uint16_t branchid = EmitCompareAndBranch(rn, static_cast<uint16_t>(label->position_), true);
2101 // cmp rn, #0
2195 void Thumb2Assembler::Lsl(Register rd, Register rm, Register rn,
2198 EmitShift(rd, rm, LSL, rn, setcc);
2202 void Thumb2Assembler::Lsr(Register rd, Register rm, Register rn,
2205 EmitShift(rd, rm, LSR, rn, setcc);
2209 void Thumb2Assembler::Asr(Register rd, Register rm, Register rn,
2212 EmitShift(rd, rm, ASR, rn, setcc);
2216 void Thumb2Assembler::Ror(Register rd, Register rm, Register rn,
2219 EmitShift(rd, rm, ROR, rn, setcc);
2295 void Thumb2Assembler::AddConstant(Register rd, Register rn, int32_t value,
2298 if (rd != rn) {
2299 mov(rd, ShifterOperand(rn), cond);
2307 if (ShifterOperand::CanHoldThumb(rd, rn, ADD, value, &shifter_op)) {
2308 add(rd, rn, shifter_op, cond);
2309 } else if (ShifterOperand::CanHoldThumb(rd, rn, SUB, -value, &shifter_op)) {
2310 sub(rd, rn, shifter_op, cond);
2312 CHECK(rn != IP);
2313 if (ShifterOperand::CanHoldThumb(rd, rn, MVN, ~value, &shifter_op)) {
2315 add(rd, rn, ShifterOperand(IP), cond);
2316 } else if (ShifterOperand::CanHoldThumb(rd, rn, MVN, ~(-value), &shifter_op)) {
2318 sub(rd, rn, ShifterOperand(IP), cond);
2325 add(rd, rn, ShifterOperand(IP), cond);
2331 void Thumb2Assembler::AddConstantSetFlags(Register rd, Register rn, int32_t value,
2334 if (ShifterOperand::CanHoldThumb(rd, rn, ADD, value, &shifter_op)) {
2335 adds(rd, rn, shifter_op, cond);
2336 } else if (ShifterOperand::CanHoldThumb(rd, rn, ADD, -value, &shifter_op)) {
2337 subs(rd, rn, shifter_op, cond);
2339 CHECK(rn != IP);
2340 if (ShifterOperand::CanHoldThumb(rd, rn, MVN, ~value, &shifter_op)) {
2342 adds(rd, rn, ShifterOperand(IP), cond);
2343 } else if (ShifterOperand::CanHoldThumb(rd, rn, MVN, ~(-value), &shifter_op)) {
2345 subs(rd, rn, ShifterOperand(IP), cond);
2352 adds(rd, rn, ShifterOperand(IP), cond);
