Lines Matching refs:Operand
264 EmitOperand(0, Operand(dst));
300 EmitOperand(dst, Operand(src));
309 EmitOperand(src, Operand(dst));
503 EmitOperand(dst, Operand(src));
512 EmitOperand(dst, Operand(src));
757 EmitComplex(7, Operand(reg), imm);
764 EmitOperand(reg0, Operand(reg1));
835 EmitOperand(0, Operand(reg));
844 EmitOperand(dst, Operand(src));
850 EmitComplex(4, Operand(dst), imm);
857 EmitOperand(dst, Operand(src));
863 EmitComplex(1, Operand(dst), imm);
870 EmitOperand(dst, Operand(src));
875 EmitComplex(6, Operand(dst), imm);
880 EmitComplex(0, Operand(reg), imm);
899 EmitComplex(2, Operand(reg), imm);
906 EmitOperand(dst, Operand(src));
920 EmitOperand(dst, Operand(src));
926 EmitComplex(5, Operand(reg), imm);
954 EmitOperand(dst, Operand(src));
961 EmitOperand(reg, Operand(reg));
977 EmitOperand(5, Operand(reg));
991 EmitOperand(4, Operand(reg));
1005 EmitOperand(dst, Operand(src));
1011 EmitComplex(3, Operand(reg), imm);
1053 void X86Assembler::shll(Register operand, Register shifter) {
1054 EmitGenericShift(4, operand, shifter);
1063 void X86Assembler::shrl(Register operand, Register shifter) {
1064 EmitGenericShift(5, operand, shifter);
1073 void X86Assembler::sarl(Register operand, Register shifter) {
1074 EmitGenericShift(7, operand, shifter);
1089 EmitOperand(3, Operand(reg));
1324 void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
1327 const int length = operand.length_;
1330 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
1331 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
1332 // Emit the rest of the encoded operand.
1334 EmitUint8(operand.encoding_[i]);
1345 const Operand& operand,
1352 EmitOperand(reg_or_opcode, operand);
1354 } else if (operand.IsRegister(EAX)) {
1360 EmitOperand(reg_or_opcode, operand);
1392 EmitOperand(reg_or_opcode, Operand(reg));
1395 EmitOperand(reg_or_opcode, Operand(reg));
1402 Register operand,
1407 EmitOperand(reg_or_opcode, Operand(operand));
