Lines Matching refs:Operand
337 EmitOperand(dst.LowBits(), Operand(src));
347 EmitOperand(src.LowBits(), Operand(dst));
561 EmitOperand(dst.LowBits(), Operand(src));
571 EmitOperand(dst.LowBits(), Operand(src));
829 EmitOperand(dst.LowBits(), Operand(src));
844 EmitComplex(7, Operand(reg), imm);
852 EmitOperand(reg0.LowBits(), Operand(reg1));
868 EmitOperand(reg0.LowBits(), Operand(reg1));
876 EmitComplex(7, Operand(reg), imm);
947 EmitOperand(0, Operand(reg));
965 EmitOperand(dst.LowBits(), Operand(src));
972 EmitComplex(4, Operand(dst), imm);
980 EmitComplex(4, Operand(reg), imm);
988 EmitOperand(dst.LowBits(), Operand(src));
995 EmitComplex(1, Operand(dst), imm);
1003 EmitOperand(dst.LowBits(), Operand(src));
1011 EmitOperand(dst.LowBits(), Operand(src));
1019 EmitComplex(6, Operand(dst), imm);
1025 // W - 64-bit operand
1052 // W - 64-bit operand
1078 EmitComplex(0, Operand(reg), imm);
1086 EmitComplex(0, Operand(reg), imm);
1126 EmitOperand(dst.LowBits(), Operand(src));
1133 EmitComplex(5, Operand(reg), imm);
1141 EmitComplex(5, Operand(reg), imm);
1188 EmitOperand(dst.LowBits(), Operand(src));
1196 EmitOperand(reg.LowBits(), Operand(reg));
1214 EmitOperand(5, Operand(reg));
1230 EmitOperand(4, Operand(reg));
1248 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) {
1249 EmitGenericShift(4, operand, shifter);
1263 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) {
1264 EmitGenericShift(5, operand, shifter);
1273 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) {
1274 EmitGenericShift(7, operand, shifter);
1282 EmitOperand(3, Operand(reg));
1520 void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) {
1523 const int length = operand.length_;
1526 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
1527 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
1528 // Emit the rest of the encoded operand.
1530 EmitUint8(operand.encoding_[i]);
1545 const Operand& operand,
1552 EmitOperand(reg_or_opcode, operand);
1554 } else if (operand.IsRegister(CpuRegister(RAX))) {
1560 EmitOperand(reg_or_opcode, operand);
1596 EmitOperand(reg_or_opcode, Operand(reg));
1599 EmitOperand(reg_or_opcode, Operand(reg));
1606 CpuRegister operand,
1611 EmitOperand(reg_or_opcode, Operand(operand));
1616 // W - 64-bit operand
1658 void X86_64Assembler::EmitOptionalRex32(const Operand& operand) {
1659 uint8_t rex = operand.rex();
1665 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) {
1666 uint8_t rex = operand.rex();
1675 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, const Operand& operand) {
1676 uint8_t rex = operand.rex();
1693 void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {
1694 uint8_t rex = 0x48 | operand.rex(); // REX.W000
1707 void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) {
1708 uint8_t rex = 0x40 | operand.rex(); // REX.0000
