Lines Matching refs:Rn
91 void FormatNeonMemory(int Rn, int align, int Rm);
303 if (format[1] == 'n') { // 'rn: Rn register
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
418 "[r%d", Rn);
712 // Rn field to encode it.
713 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
717 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
718 // Rn field to encode the Rd register and the Rd field to encode
719 // the Rn register.
720 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
723 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
724 // Rn field to encode the Rd register and the Rd field to encode
725 // the Rn register.
726 Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
731 // when referring to the target registers. They are mapped to the Rn
734 // RdHi == Rn field
736 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
746 Format(instr, "'memop'cond's 'rd, ['rn], -'rm");
748 Format(instr, "'memop'cond's 'rd, ['rn], #-'off8");
754 Format(instr, "'memop'cond's 'rd, ['rn], +'rm");
756 Format(instr, "'memop'cond's 'rd, ['rn], #+'off8");
762 Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w");
764 Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w");
770 Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w");
772 Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w");
787 Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
789 Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
795 Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
797 Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
803 Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
805 Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
811 Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
813 Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
858 Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
862 Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
866 Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
870 Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
874 Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
878 Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
882 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
886 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op");
891 Format(instr, "tst'cond 'rn, 'shift_op");
899 Format(instr, "teq'cond 'rn, 'shift_op");
909 Format(instr, "cmp'cond 'rn, 'shift_op");
917 Format(instr, "cmn'cond 'rn, 'shift_op");
926 Format(instr, "orr'cond's 'rd, 'rn, 'shift_op");
934 Format(instr, "bic'cond's 'rd, 'rn, 'shift_op");
958 Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
966 Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
970 Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
974 Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
990 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
995 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
1002 Format(instr, "pkhbt'cond 'rd, 'rn, 'rm, lsl #'imm05@07");
1005 Format(instr, "pkhtb'cond 'rd, 'rn, 'rm, asr #32");
1007 Format(instr, "pkhtb'cond 'rd, 'rn, 'rm, asr #'imm05@07");
1076 Format(instr, "uxtab'cond 'rd, 'rn, 'rm");
1079 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #8");
1082 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #16");
1085 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #24");
1103 // UDIV (in V8 notation matching ARM ISA format) rn = rm/rs
1104 Format(instr, "udiv'cond'b 'rn, 'rm, 'rs");
1106 // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs
1107 Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs");
1113 Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
1143 Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
1162 Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
1164 Format(instr, "stm'cond'pu 'rn'w, 'rlist");
1458 Format(instr, "vldr'cond 'Sd, ['rn - 4*'imm08@00]");
1460 Format(instr, "vstr'cond 'Sd, ['rn - 4*'imm08@00]");
1466 Format(instr, "vldr'cond 'Sd, ['rn + 4*'imm08@00]");
1468 Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]");
1479 Format(instr, "vldm'cond'pu 'rn'w, {'Sd-'Sd+}");
1481 Format(instr, "vstm'cond'pu 'rn'w, {'Sd-'Sd+}");
1495 Format(instr, "vmov'cond 'rt, 'rn, 'Dm");
1497 Format(instr, "vmov'cond 'Dm, 'rt, 'rn");
1503 Format(instr, "vldr'cond 'Dd, ['rn - 4*'imm08@00]");
1505 Format(instr, "vstr'cond 'Dd, ['rn - 4*'imm08@00]");
1511 Format(instr, "vldr'cond 'Dd, ['rn + 4*'imm08@00]");
1513 Format(instr, "vstr'cond 'Dd, ['rn + 4*'imm08@00]");
1524 Format(instr, "vldm'cond'pu 'rn'w, {'Dd-'Dd+}");
1526 Format(instr, "vstm'cond'pu 'rn'w, {'Dd-'Dd+}");
1573 int Rn = instr->VnValue();
1582 FormatNeonMemory(Rn, align, Rm);
1586 int Rn = instr->VnValue();
1595 FormatNeonMemory(Rn, align, Rm);
1603 int Rn = instr->Bits(19, 16);
1607 "pld [r%d]", Rn);
1610 "pld [r%d, #-%d]", Rn, offset);
1613 "pld [r%d, #+%d]", Rn, offset);
