Lines Matching defs:rn
899 instr->following()->Rn() == xzr.code()));
935 Emit(BLR | Rn(xzr));
956 Emit(BR | Rn(xn));
966 Emit(BLR | Rn(xn));
973 Emit(RET | Rn(xn));
1085 const Register& rn,
1087 AddSub(rd, rn, operand, LeaveFlags, ADD);
1092 const Register& rn,
1094 AddSub(rd, rn, operand, SetFlags, ADD);
1098 void Assembler::cmn(const Register& rn,
1100 Register zr = AppropriateZeroRegFor(rn);
1101 adds(zr, rn, operand);
1106 const Register& rn,
1108 AddSub(rd, rn, operand, LeaveFlags, SUB);
1113 const Register& rn,
1115 AddSub(rd, rn, operand, SetFlags, SUB);
1119 void Assembler::cmp(const Register& rn, const Operand& operand) {
1120 Register zr = AppropriateZeroRegFor(rn);
1121 subs(zr, rn, operand);
1138 const Register& rn,
1140 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
1145 const Register& rn,
1147 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
1152 const Register& rn,
1154 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
1159 const Register& rn,
1161 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
1179 const Register& rn,
1181 Logical(rd, rn, operand, AND);
1186 const Register& rn,
1188 Logical(rd, rn, operand, ANDS);
1192 void Assembler::tst(const Register& rn,
1194 ands(AppropriateZeroRegFor(rn), rn, operand);
1199 const Register& rn,
1201 Logical(rd, rn, operand, BIC);
1206 const Register& rn,
1208 Logical(rd, rn, operand, BICS);
1213 const Register& rn,
1215 Logical(rd, rn, operand, ORR);
1220 const Register& rn,
1222 Logical(rd, rn, operand, ORN);
1227 const Register& rn,
1229 Logical(rd, rn, operand, EOR);
1234 const Register& rn,
1236 Logical(rd, rn, operand, EON);
1241 const Register& rn,
1243 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1245 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
1250 const Register& rn,
1252 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1254 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
1259 const Register& rn,
1261 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1263 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
1268 const Register& rn,
1270 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1272 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
1278 const Register& rn,
1281 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1285 ImmS(imms, rn.SizeInBits()) |
1286 Rn(rn) | Rd(rd));
1291 const Register& rn,
1294 DCHECK(rd.Is64Bits() || rn.Is32Bits());
1298 ImmS(imms, rn.SizeInBits()) |
1299 Rn(rn) | Rd(rd));
1304 const Register& rn,
1307 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1311 ImmS(imms, rn.SizeInBits()) |
1312 Rn(rn) | Rd(rd));
1317 const Register& rn,
1320 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1324 ImmS(lsb, rn.SizeInBits()) | Rn(rn) | Rd(rd));
1329 const Register& rn,
1332 ConditionalSelect(rd, rn, rm, cond, CSEL);
1337 const Register& rn,
1340 ConditionalSelect(rd, rn, rm, cond, CSINC);
1345 const Register& rn,
1348 ConditionalSelect(rd, rn, rm, cond, CSINV);
1353 const Register& rn,
1356 ConditionalSelect(rd, rn, rm, cond, CSNEG);
1374 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) {
1376 csinc(rd, rn, rn, NegateCondition(cond));
1380 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) {
1382 csinv(rd, rn, rn, NegateCondition(cond));
1386 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) {
1388 csneg(rd, rn, rn, NegateCondition(cond));
1393 const Register& rn,
1397 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1399 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
1403 void Assembler::ccmn(const Register& rn,
1407 ConditionalCompare(rn, operand, nzcv, cond, CCMN);
1411 void Assembler::ccmp(const Register& rn,
1415 ConditionalCompare(rn, operand, nzcv, cond, CCMP);
1420 const Register& rn,
1424 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
1429 const Register& rn,
1431 DCHECK(AreSameSizeAndType(rd, rn, rm));
1432 Register zr = AppropriateZeroRegFor(rn);
1433 DataProcessing3Source(rd, rn, rm, zr, MADD);
1438 const Register& rn,
1441 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1442 DataProcessing3Source(rd, rn, rm, ra, MADD);
1447 const Register& rn,
1449 DCHECK(AreSameSizeAndType(rd, rn, rm));
1450 Register zr = AppropriateZeroRegFor(rn);
1451 DataProcessing3Source(rd, rn, rm, zr, MSUB);
1456 const Register& rn,
1459 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1460 DataProcessing3Source(rd, rn, rm, ra, MSUB);
1465 const Register& rn,
1469 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1470 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
1475 const Register& rn,
1479 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1480 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
1485 const Register& rn,
1489 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1490 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
1495 const Register& rn,
1499 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1500 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
1505 const Register& rn,
1508 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1509 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
1514 const Register& rn,
1516 DCHECK(AreSameSizeAndType(rd, rn, rm));
1517 DataProcessing3Source(rd, rn, rm, xzr, SMULH_x);
1522 const Register& rn,
1524 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1526 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
1531 const Register& rn,
1533 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1535 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
1540 const Register& rn) {
1541 DataProcessing1Source(rd, rn, RBIT);
1546 const Register& rn) {
1547 DataProcessing1Source(rd, rn, REV16);
1552 const Register& rn) {
1554 DataProcessing1Source(rd, rn, REV);
1559 const Register& rn) {
1560 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w);
1565 const Register& rn) {
1566 DataProcessing1Source(rd, rn, CLZ);
1571 const Register& rn) {
1572 DataProcessing1Source(rd, rn, CLS);
1792 Emit(op | Rd(rd) | Rn(fn));
1796 void Assembler::fmov(FPRegister fd, Register rn) {
1797 DCHECK(fd.SizeInBits() == rn.SizeInBits());
1799 Emit(op | Rd(fd) | Rn(rn));
1805 Emit(FPType(fd) | FMOV | Rd(fd) | Rn(fn));
1949 Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn));
1960 Emit(FPType(fn) | FCMP_zero | Rn(fn));
1969 Emit(FPType(fn) | FCCMP | Rm(fm) | Cond(cond) | Rn(fn) | Nzcv(nzcv));
1979 Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd));
1986 Emit(SF(rd) | FPType(fn) | op | Rn(fn) | Rd(rd));
2045 const Register& rn,
2048 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd));
2050 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2057 const Register& rn,
2060 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd));
2062 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2150 const Register& rn,
2154 DCHECK(rd.SizeInBits() == rn.SizeInBits());
2161 ImmAddSub(immediate) | dest_reg | RnSP(rn));
2173 if (rn.IsSP() || rd.IsSP()) {
2175 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
2178 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
2182 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
2188 const Register& rn,
2192 DCHECK(rd.SizeInBits() == rn.SizeInBits());
2196 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
2258 const Register& rn,
2261 DCHECK(rd.SizeInBits() == rn.SizeInBits());
2280 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
2289 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
2295 const Register& rn,
2304 Rn(rn));
2308 void Assembler::ConditionalCompare(const Register& rn,
2323 Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv));
2328 const Register& rn,
2330 DCHECK(rd.SizeInBits() == rn.SizeInBits());
2331 Emit(SF(rn) | op | Rn(rn) | Rd(rd));
2338 Emit(FPType(fn) | op | Rn(fn) | Rd(fd));
2348 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd));
2358 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));
2363 const Register& rn,
2368 lsl(rd, rn, shift_amount);
2371 lsr(rd, rn, shift_amount);
2374 asr(rd, rn, shift_amount);
2377 ror(rd, rn, shift_amount);
2386 const Register& rn,
2389 DCHECK(rd.SizeInBits() >= rn.SizeInBits());
2392 Register rn_ = Register::Create(rn.code(), rd.SizeInBits());
2408 DCHECK(rn.SizeInBits() == kXRegSizeInBits);
2423 const Register& rn,
2428 DCHECK(rn.Is64Bits() || (rn.Is32Bits() && is_uint5(operand.shift_amount())));
2432 Rm(operand.reg()) | Rn(rn) | Rd(rd));
2437 const Register& rn,
2445 dest_reg | RnSP(rn));
