Lines Matching refs:Rd
522 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
538 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
1073 void Assembler::adr(const Register& rd, int imm21) {
1074 DCHECK(rd.Is64Bits());
1075 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
1079 void Assembler::adr(const Register& rd, Label* label) {
1080 adr(rd, LinkAndGetByteOffsetTo(label));
1084 void Assembler::add(const Register& rd,
1087 AddSub(rd, rn, operand, LeaveFlags, ADD);
1091 void Assembler::adds(const Register& rd,
1094 AddSub(rd, rn, operand, SetFlags, ADD);
1105 void Assembler::sub(const Register& rd,
1108 AddSub(rd, rn, operand, LeaveFlags, SUB);
1112 void Assembler::subs(const Register& rd,
1115 AddSub(rd, rn, operand, SetFlags, SUB);
1125 void Assembler::neg(const Register& rd, const Operand& operand) {
1126 Register zr = AppropriateZeroRegFor(rd);
1127 sub(rd, zr, operand);
1131 void Assembler::negs(const Register& rd, const Operand& operand) {
1132 Register zr = AppropriateZeroRegFor(rd);
1133 subs(rd, zr, operand);
1137 void Assembler::adc(const Register& rd,
1140 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
1144 void Assembler::adcs(const Register& rd,
1147 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
1151 void Assembler::sbc(const Register& rd,
1154 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
1158 void Assembler::sbcs(const Register& rd,
1161 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
1165 void Assembler::ngc(const Register& rd, const Operand& operand) {
1166 Register zr = AppropriateZeroRegFor(rd);
1167 sbc(rd, zr, operand);
1171 void Assembler::ngcs(const Register& rd, const Operand& operand) {
1172 Register zr = AppropriateZeroRegFor(rd);
1173 sbcs(rd, zr, operand);
1178 void Assembler::and_(const Register& rd,
1181 Logical(rd, rn, operand, AND);
1185 void Assembler::ands(const Register& rd,
1188 Logical(rd, rn, operand, ANDS);
1198 void Assembler::bic(const Register& rd,
1201 Logical(rd, rn, operand, BIC);
1205 void Assembler::bics(const Register& rd,
1208 Logical(rd, rn, operand, BICS);
1212 void Assembler::orr(const Register& rd,
1215 Logical(rd, rn, operand, ORR);
1219 void Assembler::orn(const Register& rd,
1222 Logical(rd, rn, operand, ORN);
1226 void Assembler::eor(const Register& rd,
1229 Logical(rd, rn, operand, EOR);
1233 void Assembler::eon(const Register& rd,
1236 Logical(rd, rn, operand, EON);
1240 void Assembler::lslv(const Register& rd,
1243 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1244 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1245 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
1249 void Assembler::lsrv(const Register& rd,
1252 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1253 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1254 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
1258 void Assembler::asrv(const Register& rd,
1261 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1262 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1263 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
1267 void Assembler::rorv(const Register& rd,
1270 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1271 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1272 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
1277 void Assembler::bfm(const Register& rd,
1281 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1282 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
1283 Emit(SF(rd) | BFM | N |
1284 ImmR(immr, rd.SizeInBits()) |
1286 Rn(rn) | Rd(rd));
1290 void Assembler::sbfm(const Register& rd,
1294 DCHECK(rd.Is64Bits() || rn.Is32Bits());
1295 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
1296 Emit(SF(rd) | SBFM | N |
1297 ImmR(immr, rd.SizeInBits()) |
1299 Rn(rn) | Rd(rd));
1303 void Assembler::ubfm(const Register& rd,
1307 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1308 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
1309 Emit(SF(rd) | UBFM | N |
1310 ImmR(immr, rd.SizeInBits()) |
1312 Rn(rn) | Rd(rd));
1316 void Assembler::extr(const Register& rd,
1320 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1321 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1322 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
1323 Emit(SF(rd) | EXTR | N | Rm(rm) |
1324 ImmS(lsb, rn.SizeInBits()) | Rn(rn) | Rd(rd));
1328 void Assembler::csel(const Register& rd,
1332 ConditionalSelect(rd, rn, rm, cond, CSEL);
1336 void Assembler::csinc(const Register& rd,
1340 ConditionalSelect(rd, rn, rm, cond, CSINC);
1344 void Assembler::csinv(const Register& rd,
1348 ConditionalSelect(rd, rn, rm, cond, CSINV);
1352 void Assembler::csneg(const Register& rd,
1356 ConditionalSelect(rd, rn, rm, cond, CSNEG);
1360 void Assembler::cset(const Register &rd, Condition cond) {
1362 Register zr = AppropriateZeroRegFor(rd);
1363 csinc(rd, zr, zr, NegateCondition(cond));
1367 void Assembler::csetm(const Register &rd, Condition cond) {
1369 Register zr = AppropriateZeroRegFor(rd);
1370 csinv(rd, zr, zr, NegateCondition(cond));
1374 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) {
1376 csinc(rd, rn, rn, NegateCondition(cond));
1380 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) {
1382 csinv(rd, rn, rn, NegateCondition(cond));
1386 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) {
1388 csneg(rd, rn, rn, NegateCondition(cond));
1392 void Assembler::ConditionalSelect(const Register& rd,
1397 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1398 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1399 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
1419 void Assembler::DataProcessing3Source(const Register& rd,
1424 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
1428 void Assembler::mul(const Register& rd,
1431 DCHECK(AreSameSizeAndType(rd, rn, rm));
1433 DataProcessing3Source(rd, rn, rm, zr, MADD);
1437 void Assembler::madd(const Register& rd,
1441 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1442 DataProcessing3Source(rd, rn, rm, ra, MADD);
1446 void Assembler::mneg(const Register& rd,
1449 DCHECK(AreSameSizeAndType(rd, rn, rm));
1451 DataProcessing3Source(rd, rn, rm, zr, MSUB);
1455 void Assembler::msub(const Register& rd,
1459 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1460 DataProcessing3Source(rd, rn, rm, ra, MSUB);
1464 void Assembler::smaddl(const Register& rd,
1468 DCHECK(rd.Is64Bits() && ra.Is64Bits());
1470 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
1474 void Assembler::smsubl(const Register& rd,
1478 DCHECK(rd.Is64Bits() && ra.Is64Bits());
1480 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
1484 void Assembler::umaddl(const Register& rd,
1488 DCHECK(rd.Is64Bits() && ra.Is64Bits());
1490 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
1494 void Assembler::umsubl(const Register& rd,
1498 DCHECK(rd.Is64Bits() && ra.Is64Bits());
1500 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
1504 void Assembler::smull(const Register& rd,
1507 DCHECK(rd.Is64Bits());
1509 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
1513 void Assembler::smulh(const Register& rd,
1516 DCHECK(AreSameSizeAndType(rd, rn, rm));
1517 DataProcessing3Source(rd, rn, rm, xzr, SMULH_x);
1521 void Assembler::sdiv(const Register& rd,
1524 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1525 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1526 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
1530 void Assembler::udiv(const Register& rd,
1533 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1534 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1535 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
1539 void Assembler::rbit(const Register& rd,
1541 DataProcessing1Source(rd, rn, RBIT);
1545 void Assembler::rev16(const Register& rd,
1547 DataProcessing1Source(rd, rn, REV16);
1551 void Assembler::rev32(const Register& rd,
1553 DCHECK(rd.Is64Bits());
1554 DataProcessing1Source(rd, rn, REV);
1558 void Assembler::rev(const Register& rd,
1560 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w);
1564 void Assembler::clz(const Register& rd,
1566 DataProcessing1Source(rd, rn, CLZ);
1570 void Assembler::cls(const Register& rd,
1572 DataProcessing1Source(rd, rn, CLS);
1726 void Assembler::mov(const Register& rd, const Register& rm) {
1730 if (rd.IsSP() || rm.IsSP()) {
1731 add(rd, rm, 0);
1733 orr(rd, AppropriateZeroRegFor(rd), rm);
1738 void Assembler::mvn(const Register& rd, const Operand& operand) {
1739 orn(rd, AppropriateZeroRegFor(rd), operand);
1778 Emit(FMOV_d_imm | Rd(fd) | ImmFP64(imm));
1785 Emit(FMOV_s_imm | Rd(fd) | ImmFP32(imm));
1789 void Assembler::fmov(Register rd, FPRegister fn) {
1790 DCHECK(rd.SizeInBits() == fn.SizeInBits());
1791 FPIntegerConvertOp op = rd.Is32Bits() ? FMOV_ws : FMOV_xd;
1792 Emit(op | Rd(rd) | Rn(fn));
1799 Emit(op | Rd(fd) | Rn(rn));
1805 Emit(FPType(fd) | FMOV | Rd(fd) | Rn(fn));
1979 Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd));
1983 void Assembler::FPConvertToInt(const Register& rd,
1986 Emit(SF(rd) | FPType(fn) | op | Rn(fn) | Rd(rd));
2004 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) {
2005 FPConvertToInt(rd, fn, FCVTAU);
2009 void Assembler::fcvtas(const Register& rd, const FPRegister& fn) {
2010 FPConvertToInt(rd, fn, FCVTAS);
2014 void Assembler::fcvtmu(const Register& rd, const FPRegister& fn) {
2015 FPConvertToInt(rd, fn, FCVTMU);
2019 void Assembler::fcvtms(const Register& rd, const FPRegister& fn) {
2020 FPConvertToInt(rd, fn, FCVTMS);
2024 void Assembler::fcvtnu(const Register& rd, const FPRegister& fn) {
2025 FPConvertToInt(rd, fn, FCVTNU);
2029 void Assembler::fcvtns(const Register& rd, const FPRegister& fn) {
2030 FPConvertToInt(rd, fn, FCVTNS);
2034 void Assembler::fcvtzu(const Register& rd, const FPRegister& fn) {
2035 FPConvertToInt(rd, fn, FCVTZU);
2039 void Assembler::fcvtzs(const Register& rd, const FPRegister& fn) {
2040 FPConvertToInt(rd, fn, FCVTZS);
2048 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd));
2051 Rd(fd));
2060 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd));
2063 Rd(fd));
2104 void Assembler::MoveWide(const Register& rd,
2109 if (rd.Is32Bits()) {
2120 DCHECK(rd.Is64Bits() || (shift == 0) || (shift == 16));
2132 DCHECK(rd.Is64Bits());
2136 DCHECK(rd.Is64Bits());
2144 Emit(SF(rd) | MoveWideImmediateFixed | mov_op |
2145 Rd(rd) | ImmMoveWide(imm) | ShiftMoveWide(shift));
2149 void Assembler::AddSub(const Register& rd,
2154 DCHECK(rd.SizeInBits() == rn.SizeInBits());
2159 Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd);
2160 Emit(SF(rd) | AddSubImmediateFixed | op | Flags(S) |
2163 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
2173 if (rn.IsSP() || rd.IsSP()) {
2174 DCHECK(!(rd.IsSP() && (S == SetFlags)));
2175 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
2178 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
2182 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
2187 void Assembler::AddSubWithCarry(const Register& rd,
2192 DCHECK(rd.SizeInBits() == rn.SizeInBits());
2193 DCHECK(rd.SizeInBits() == operand.reg().SizeInBits());
2196 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
2257 void Assembler::Logical(const Register& rd,
2261 DCHECK(rd.SizeInBits() == rn.SizeInBits());
2265 unsigned reg_size = rd.SizeInBits();
2269 DCHECK(rd.Is64Bits() || is_uint32(immediate));
2274 immediate = rd.Is64Bits() ? ~immediate : (~immediate & kWRegMask);
2280 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
2287 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
2289 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
2294 void Assembler::LogicalImmediate(const Register& rd,
2300 unsigned reg_size = rd.SizeInBits();
2301 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd);
2302 Emit(SF(rd) | LogicalImmediateFixed | op | BitN(n, reg_size) |
2327 void Assembler::DataProcessing1Source(const Register& rd,
2330 DCHECK(rd.SizeInBits() == rn.SizeInBits());
2331 Emit(SF(rn) | op | Rn(rn) | Rd(rd));
2338 Emit(FPType(fn) | op | Rn(fn) | Rd(fd));
2348 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd));
2358 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));
2362 void Assembler::EmitShift(const Register& rd,
2368 lsl(rd, rn, shift_amount);
2371 lsr(rd, rn, shift_amount);
2374 asr(rd, rn, shift_amount);
2377 ror(rd, rn, shift_amount);
2385 void Assembler::EmitExtendShift(const Register& rd,
2389 DCHECK(rd.SizeInBits() >= rn.SizeInBits());
2390 unsigned reg_size = rd.SizeInBits();
2392 Register rn_ = Register::Create(rn.code(), rd.SizeInBits());
2402 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break;
2405 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break;
2410 lsl(rd, rn_, left_shift);
2417 lsl(rd, rn_, left_shift);
2422 void Assembler::DataProcShiftedRegister(const Register& rd,
2430 Emit(SF(rd) | op | Flags(S) |
2432 Rm(operand.reg()) | Rn(rn) | Rd(rd));
2436 void Assembler::DataProcExtendedRegister(const Register& rd,
2442 Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd);
2443 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
3108 // adr rd, 0
3116 int rd_code = expected_adr->Rd();
3125 int scratch_code = expected_movz->Rd();
3128 Register rd = Register::XRegFromCode(rd_code);
3131 adr(rd, target_offset & 0xFFFF);
3135 add(rd, rd, scratch);
