Lines Matching refs:Rm
1242 const Register& rm) {
1244 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1245 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
1251 const Register& rm) {
1253 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1254 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
1260 const Register& rm) {
1262 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1263 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
1269 const Register& rm) {
1271 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1272 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
1318 const Register& rm,
1321 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1323 Emit(SF(rd) | EXTR | N | Rm(rm) |
1330 const Register& rm,
1332 ConditionalSelect(rd, rn, rm, cond, CSEL);
1338 const Register& rm,
1340 ConditionalSelect(rd, rn, rm, cond, CSINC);
1346 const Register& rm,
1348 ConditionalSelect(rd, rn, rm, cond, CSINV);
1354 const Register& rm,
1356 ConditionalSelect(rd, rn, rm, cond, CSNEG);
1394 const Register& rm,
1398 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1399 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
1421 const Register& rm,
1424 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
1430 const Register& rm) {
1431 DCHECK(AreSameSizeAndType(rd, rn, rm));
1433 DataProcessing3Source(rd, rn, rm, zr, MADD);
1439 const Register& rm,
1441 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1442 DataProcessing3Source(rd, rn, rm, ra, MADD);
1448 const Register& rm) {
1449 DCHECK(AreSameSizeAndType(rd, rn, rm));
1451 DataProcessing3Source(rd, rn, rm, zr, MSUB);
1457 const Register& rm,
1459 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1460 DataProcessing3Source(rd, rn, rm, ra, MSUB);
1466 const Register& rm,
1469 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1470 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
1476 const Register& rm,
1479 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1480 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
1486 const Register& rm,
1489 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1490 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
1496 const Register& rm,
1499 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1500 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
1506 const Register& rm) {
1508 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1509 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
1515 const Register& rm) {
1516 DCHECK(AreSameSizeAndType(rd, rn, rm));
1517 DataProcessing3Source(rd, rn, rm, xzr, SMULH_x);
1523 const Register& rm) {
1525 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1526 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
1532 const Register& rm) {
1534 DCHECK(rd.SizeInBits() == rm.SizeInBits());
1535 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
1726 void Assembler::mov(const Register& rd, const Register& rm) {
1730 if (rd.IsSP() || rm.IsSP()) {
1731 add(rd, rm, 0);
1733 orr(rd, AppropriateZeroRegFor(rd), rm);
1949 Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn));
1969 Emit(FPType(fn) | FCCMP | Rm(fm) | Cond(cond) | Rn(fn) | Nzcv(nzcv));
1979 Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd));
2196 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
2321 ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.reg());
2348 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd));
2358 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));
2432 Rm(operand.reg()) | Rn(rn) | Rd(rd));
2443 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
2487 Emit(LoadStoreRegisterOffsetFixed | memop | Rm(addr.regoffset()) |
