Lines Matching defs:lui
205 // specially coded on MIPS means that it is a lui/ori instruction, and that is
575 return opcode == LUI;
1660 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);
1766 void Assembler::lui(Register rd, int32_t j) {
1768 GenInstrImmediate(LUI, zero_reg, rd, j);
1773 // This instruction uses same opcode as 'lui'. The difference in encoding is
1774 // 'lui' has zero reg. for rs field.
1776 GenInstrImmediate(LUI, rs, rt, j);
2532 lui(at, (imm32 & kHiMask) >> kLuiShift);
2559 // Interpret 2 instructions generated by li: lui/ori
2560 if ((GetOpcodeField(instr1) == LUI) && (GetOpcodeField(instr2) == ORI)) {
2581 // On Mips, a target address is stored in a lui/ori instruction pair, each
2599 CHECK((GetOpcodeField(instr1) == LUI && GetOpcodeField(instr2) == ORI));
2602 // Must use 2 instructions to insure patchable code => just use lui and ori.
2603 // lui rt, upper-16.
2605 *p = LUI | rt_code | ((itarget & kHiMask) >> kLuiShift);
2695 // Address pc points to lui/ori instructions.
2706 DCHECK(GetOpcodeField(instr1) == LUI);
2714 DCHECK(GetOpcodeField(instr1) == LUI);
