Lines Matching refs:ORI
205 // specially coded on MIPS means that it is a lui/ori instruction, and that is
582 return opcode == ORI;
1574 void Assembler::ori(Register rt, Register rs, int32_t j) {
1576 GenInstrImmediate(ORI, rs, rt, j);
1661 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
2533 ori(at, at, (imm32 & kImm16Mask));
2559 // Interpret 2 instructions generated by li: lui/ori
2560 if ((GetOpcodeField(instr1) == LUI) && (GetOpcodeField(instr2) == ORI)) {
2581 // On Mips, a target address is stored in a lui/ori instruction pair, each
2599 CHECK((GetOpcodeField(instr1) == LUI && GetOpcodeField(instr2) == ORI));
2602 // Must use 2 instructions to insure patchable code => just use lui and ori.
2604 // ori rt rt, lower-16.
2606 *(p + 1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask);
2665 // JALR rs reg is the rt reg specified in the ORI instruction.
2677 // JR 'rs' reg is the 'rt' reg specified in the ORI instruction (instr2).
2695 // Address pc points to lui/ori instructions.
2707 DCHECK(GetOpcodeField(instr2) == ORI);
2715 DCHECK(GetOpcodeField(instr2) == ORI);
