Lines Matching refs:ORI
183 // specially coded on MIPS means that it is a lui/ori instruction, and that is
554 return opcode == ORI;
1638 void Assembler::ori(Register rt, Register rs, int32_t j) {
1640 GenInstrImmediate(ORI, rs, rt, j);
1788 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
2774 ori(at, at, (imm64 >> 16) & kImm16Mask);
2776 ori(at, at, imm64 & kImm16Mask);
2806 if ((GetOpcodeField(instr0) == LUI) && (GetOpcodeField(instr1) == ORI) &&
2807 (GetOpcodeField(instr3) == ORI)) {
2835 // 1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
2837 // 3: ori(rd, rd, j.imm32_ & kImm16Mask);
2839 // Patching the address must replace all the lui & ori instructions,
2862 CHECK((GetOpcodeField(instr0) == LUI && GetOpcodeField(instr1) == ORI &&
2863 GetOpcodeField(instr3) == ORI));
2868 // ori rt, rt, lower-16.
2870 // ori rt rt, lower-16.
2872 *(p + 1) = ORI | (rt_code << kRtShift) | (rt_code << kRsShift)
2874 *(p + 3) = ORI | (rt_code << kRsShift) | (rt_code << kRtShift)
2884 // Address pc points to lui/ori instructions.
2896 DCHECK(GetOpcodeField(instr2) == ORI);
2904 DCHECK(GetOpcodeField(instr2) == ORI);
