Lines Matching refs:ULL
336 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
371 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
372 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
373 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
374 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
375 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
376 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
377 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
378 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
379 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
380 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
383 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
384 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
385 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
386 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
387 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
388 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
389 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
390 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
391 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
392 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
393 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
394 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
395 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
396 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
397 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
542 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
