Lines Matching refs:Rd
618 uint32_t Rd; // the destination register
622 Rd = 7;
626 Rd = Bits32(opcode, 15, 12);
641 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr))
677 uint32_t Rd; // the destination register
680 Rd = 7;
683 Rd = 12;
690 if (Rd == GetFramePointerRegisterNumber())
698 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
740 uint32_t Rd; // the destination register
744 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
747 if (Rd == 15 && InITBlock() && !LastInITBlock())
751 Rd = Bits32(opcode, 2, 0);
758 Rd = Bits32(opcode, 11, 8);
762 if (setflags && (BadReg(Rd) || BadReg(Rm)))
765 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
769 Rd = Bits32(opcode, 15, 12);
773 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
774 if (Rd == 15 && setflags)
784 // The context specifies that Rm is to be moved into Rd.
791 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
823 uint32_t Rd; // the destination register
824 uint32_t imm32; // the immediate value to be written to Rd
831 Rd = Bits32(opcode, 10, 8);
839 Rd = Bits32(opcode, 11, 8);
842 if (BadReg(Rd))
849 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8, 32);
850 Rd = Bits32 (opcode, 11, 8);
859 if (BadReg (Rd))
865 // d = UInt(Rd); setflags = (S == ?1?); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C);
866 Rd = Bits32 (opcode, 15, 12);
870 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
871 if ((Rd == 15) && setflags)
878 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
879 Rd = Bits32 (opcode, 15, 12);
886 if (Rd == 15)
896 // The context specifies that an immediate is to be moved into Rd.
901 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
956 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
969 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1063 uint32_t Rd; // the destination register
1069 Rd = Bits32(opcode, 11, 8);
1074 Rd = Bits32(opcode, 15, 12);
1078 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1079 if (Rd == 15 && setflags)
1087 // The context specifies that an immediate is to be moved into Rd.
1092 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1125 uint32_t Rd; // the destination register
1132 Rd = Bits32(opcode, 2, 0);
1141 Rd = Bits32(opcode, 11, 8);
1146 if (BadReg(Rd) || BadReg(Rm))
1150 Rd = Bits32(opcode, 15, 12);
1168 // The context specifies that an immediate is to be moved into Rd.
1173 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1311 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
1792 // If Rd == 13 => A sub operation to adjust the SP -- allocate space for local storage.
1821 uint32_t Rd;
1826 Rd = 13;
1831 Rd = Bits32(opcode, 11, 8);
1834 if (Rd == 15 && setflags)
1836 if (Rd == 15 && !setflags)
1840 Rd = Bits32(opcode, 11, 8);
1843 if (Rd == 15)
1847 Rd = Bits32(opcode, 15, 12);
1851 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1852 if (Rd == 15 && setflags)
1861 if (Rd == 13)
1874 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
2475 // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 = ZeroExtend(imm3, 32);
2493 // if Rd == '1111' && S == '1' then SEE CMN (immediate);
2495 // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = ThumbExpandImm(i:imm3:imm8);
2511 // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
2582 uint32_t Rd, Rn;
2588 Rd = Bits32(opcode, 15, 12);
2610 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
2642 uint32_t Rd, Rn, Rm;
2649 Rd = Bits32(opcode, 2, 0);
2657 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2664 if (Rd == 15 && InITBlock() && !LastInITBlock())
2668 Rd = Bits32(opcode, 15, 12);
2701 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
3189 uint32_t Rd; // the destination register
3211 Rd = Bits32(opcode, 2, 0);
3222 Rd = Bits32(opcode, 11, 8);
3226 if (BadReg(Rd) || BadReg(Rm))
3230 Rd = Bits32(opcode, 15, 12);
3255 // The context specifies that an immediate is to be moved into Rd.
3260 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3278 uint32_t Rd; // the destination register
3285 Rd = Bits32(opcode, 2, 0);
3286 Rn = Rd;
3291 Rd = Bits32(opcode, 11, 8);
3295 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3299 Rd = Bits32(opcode, 15, 12);
3303 if (Rd == 15 || Rn == 15 || Rm == 15)
3326 // The context specifies that an immediate is to be moved into Rd.
3331 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5255 uint32_t Rd, Rn;
5261 Rd = Bits32(opcode, 11, 8);
5265 if (BadReg(Rd) || BadReg(Rn))
5269 Rd = Bits32(opcode, 15, 12);
5274 if (Rd == 15 && setflags)
5292 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
5325 uint32_t Rd, Rn, Rm;
5332 Rd = Rn = Bits32(opcode, 2, 0);
5339 Rd = Bits32(opcode, 11, 8);
5344 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5348 Rd = Bits32(opcode, 15, 12);
5354 if (Rd == 15 && setflags)
5380 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
5406 uint32_t Rd;
5412 Rd = Bits32(opcode, 10, 8);
5418 Rd = Bits32(opcode, 11, 8);
5421 if (BadReg(Rd))
5426 Rd = Bits32(opcode, 15, 12);
5445 if (!WriteCoreReg(context, result, Rd))
5476 uint32_t Rd, Rn;
5483 Rd = Bits32(opcode, 11, 8);
5487 // if Rd == '1111' && S == '1' then SEE TST (immediate);
5488 if (Rd == 15 && setflags)
5490 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
5494 Rd = Bits32(opcode, 15, 12);
5499 if (Rd == 15 && setflags)
5517 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5550 uint32_t Rd, Rn, Rm;
5558 Rd = Rn = Bits32(opcode, 2, 0);
5565 Rd = Bits32(opcode, 11, 8);
5570 // if Rd == '1111' && S == '1' then SEE TST (register);
5571 if (Rd == 15 && setflags)
5573 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
5577 Rd = Bits32(opcode, 15, 12);
5583 if (Rd == 15 && setflags)
5609 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5641 uint32_t Rd, Rn;
5648 Rd = Bits32(opcode, 11, 8);
5652 if (BadReg(Rd) || BadReg(Rn))
5656 Rd = Bits32(opcode, 15, 12);
5661 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5662 if (Rd == 15 && setflags)
5680 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5713 uint32_t Rd, Rn, Rm;
5721 Rd = Rn = Bits32(opcode, 2, 0);
5728 Rd = Bits32(opcode, 11, 8);
5733 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5737 Rd = Bits32(opcode, 15, 12);
5743 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5744 if (Rd == 15 && setflags)
5770 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
7795 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7803 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7815 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7879 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7887 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7899 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7963 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7971 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7983 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8044 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8052 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8064 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8275 uint32_t Rd, Rn;
8282 Rd = Bits32(opcode, 11, 8);
8286 // if Rd == '1111' && S == '1' then SEE TEQ (immediate);
8287 if (Rd == 15 && setflags)
8289 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
8293 Rd = Bits32(opcode, 15, 12);
8298 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8299 if (Rd == 15 && setflags)
8317 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8350 uint32_t Rd, Rn, Rm;
8358 Rd = Rn = Bits32(opcode, 2, 0);
8365 Rd = Bits32(opcode, 11, 8);
8370 // if Rd == '1111' && S == '1' then SEE TEQ (register);
8371 if (Rd == 15 && setflags)
8373 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
8377 Rd = Bits32(opcode, 15, 12);
8383 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8384 if (Rd == 15 && setflags)
8410 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8442 uint32_t Rd, Rn;
8449 Rd = Bits32(opcode, 11, 8);
8456 if (BadReg(Rd) || Rn == 13)
8460 Rd = Bits32(opcode, 15, 12);
8465 if (Rd == 15 && setflags)
8483 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8516 uint32_t Rd, Rn, Rm;
8524 Rd = Rn = Bits32(opcode, 2, 0);
8531 Rd = Bits32(opcode, 11, 8);
8539 if (BadReg(Rd) || Rn == 13 || BadReg(Rm))
8543 Rd = Bits32(opcode, 15, 12);
8549 if (Rd == 15 && setflags)
8575 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8604 uint32_t Rd; // the destination register
8610 Rd = Bits32(opcode, 2, 0);
8616 Rd = Bits32(opcode, 11, 8);
8620 if (BadReg(Rd) || BadReg(Rn))
8624 Rd = Bits32(opcode, 15, 12);
8629 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8630 if (Rd == 15 && setflags)
8647 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8677 uint32_t Rd; // the destination register
8685 Rd = Bits32(opcode, 11, 8);
8691 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8695 Rd = Bits32(opcode, 15, 12);
8701 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8702 if (Rd == 15 && setflags)
8726 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8756 uint32_t Rd; // the destination register
8762 Rd = Bits32(opcode, 15, 12);
8767 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8768 if (Rd == 15 && setflags)
8785 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8816 uint32_t Rd; // the destination register
8824 Rd = Bits32(opcode, 15, 12);
8830 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8831 if (Rd == 15 && setflags)
8855 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8885 uint32_t Rd; // the destination register
8891 Rd = Bits32(opcode, 11, 8);
8895 if (BadReg(Rd) || BadReg(Rn))
8899 Rd = Bits32(opcode, 15, 12);
8904 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8905 if (Rd == 15 && setflags)
8922 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8953 uint32_t Rd; // the destination register
8961 Rd = Rn = Bits32(opcode, 2, 0);
8968 Rd = Bits32(opcode, 11, 8);
8973 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8977 Rd = Bits32(opcode, 15, 12);
8983 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8984 if (Rd == 15 && setflags)
9008 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9034 uint32_t Rd; // the destination register
9040 Rd = Bits32(opcode, 2, 0);
9046 Rd = Rn = Bits32(opcode, 10, 8);
9051 Rd = Bits32(opcode, 11, 8);
9056 // if Rd == '1111' && S == '1' then SEE CMP (immediate);
9057 if (Rd == 15 && setflags)
9065 if (Rd == 13 || (Rd == 15 && !setflags) || Rn == 15)
9069 Rd = Bits32(opcode, 11, 8);
9082 if (BadReg(Rd))
9099 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9128 uint32_t Rd; // the destination register
9134 Rd = Bits32(opcode, 15, 12);
9147 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
9148 if (Rd == 15 && setflags)
9165 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9459 // d = UInt(Rd); m = UInt(Rm); setflags = (S == ?1?);
9477 // d = UInt(Rd); m = UInt(Rm); setflags = (S == ?1?);
9482 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
9557 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
9657 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock();
9670 // if Rd == ?1111? && S == ?1? then SEE CMP (register);
9672 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ?1?);
9689 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ?1?);
9695 // if Rd == ?1111? && S == ?1? then SEE SUBS PC, LR and related instructions;
9778 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
9795 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero offset
12283 { 0x0fef0010, 0x004d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" },
12324 { 0x0fe00000, 0x02a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"},
12326 { 0x0fe00010, 0x00a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12328 { 0x0fe00000, 0x02800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmARM, "add{s}<c> <Rd>, <Rn>, #const"},
12330 { 0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDReg, "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12332 { 0x0fe00090, 0x00800010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRegShift, "add{s}<c> <Rd>, <Rn>, <Rm>, <type> <RS>"},
12334 { 0x0fff0000, 0x028f0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12335 { 0x0fff0000, 0x024f0000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12337 { 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"},
12339 { 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12341 { 0x0fe00000, 0x03c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #const"},
12343 { 0x0fe00010, 0x01c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12345 { 0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"},
12347 { 0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12349 { 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"},
12351 { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12353 { 0x0fe00000, 0x02600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c> <Rd>, <Rn>, #<const>"},
12355 { 0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12357 { 0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"},
12359 { 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12361 { 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12363 { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12365 { 0x0fe00000, 0x02400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmARM, "sub{s}<c> <Rd>, <Rn>, #<const>"},
12367 { 0x0fef0000, 0x024d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}<c> <Rd>, sp, #<const>"},
12369 { 0x0fe00010, 0x00400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"},
12380 { 0x0fef0000, 0x03a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c> <Rd>, #<const>"},
12381 { 0x0ff00000, 0x03000000, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>, #<imm16>" },
12383 { 0x0fef0ff0, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"},
12385 { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s}<c> <Rd>, #<const>"},
12387 { 0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c> <Rd>, <Rm> {,<shift>}"},
12397 { 0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"},
12399 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
12401 { 0x0fef0070, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"},
12403 { 0x0fef00f0, 0x01a00010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
12405 { 0x0fef0070, 0x01a00020, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"},
12407 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
12409 { 0x0fef0ff0, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"},
12411 { 0x0fef0070, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"},
12413 { 0x0fef00f0, 0x01a00070, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
12415 { 0x0fe000f0, 0x00000090, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>" },
12459 { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
12474 { 0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}" },
12475 { 0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}" },
12476 { 0x0fff00f0, 0x06ef0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}" },
12477 { 0x0fff00f0, 0x06ff0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}" },
12524 { 0xffef8000, 0xebad0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" },
12534 { 0xfffff800, 0x0000a800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"},
12586 { 0xfbe08000, 0xf1400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"},
12589 { 0xffe08000, 0xeb400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12591 { 0xfffffe00, 0x00001800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
12595 { 0xfffff800, 0x0000a000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12596 { 0xfbff8000, 0xf2af0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12597 { 0xfbff8000, 0xf20f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12599 { 0xfbe08000, 0xf0000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #<const>"},
12602 { 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12604 { 0xfbe08000, 0xf0200000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #<const>"},
12607 { 0xffe08000, 0xea200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12609 { 0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"},
12612 { 0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12614 { 0xfbe08000, 0xf0400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"},
12617 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12619 { 0xffffffc0, 0x00004240, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"},
12620 { 0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c>.w <Rd>, <Rn>, #<const>"},
12622 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12624 { 0xfbe08000, 0xf1600000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12627 { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12629 { 0xfffffe00, 0x00001c00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rd>,<Rn>,#<imm3>" },
12631 { 0xfbe08000, 0xf1000000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "add{s}<c>.w <Rd>,<Rn>,#<const>" },
12632 { 0xfbf08000, 0xf2000000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "addw<c> <Rd>,<Rn>,#<imm12>" },
12634 Rd>, <Rn> #imm3"},
12636 { 0xfbe08000, 0xf1a00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "sub{s}<c>.w <Rd>, <Rn>, #<const>"},
12637 { 0xfbf08000, 0xf2a00000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "subw<c> <Rd>, <Rn>, #imm12"},
12639 { 0xfbef8000, 0xf1ad0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w <Rd>, sp, #<const>"},
12640 { 0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw<c> <Rd>, sp, #imm12"},
12642 { 0xfffffe00, 0x00001a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
12643 { 0xffe08000, 0xeba00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"},
12656 { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"},
12658 { 0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"},
12659 // mov{s}<c>.w <Rd>, <Rm>
12660 { 0xffeff0f0, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"},
12662 { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov<c> <Rd>, #imm8"},
12663 { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c>.w <Rd>, #<const>"},
12664 { 0xfbf08000, 0xf2400000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>,#<imm16>"},
12666 { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} <Rd>, #<const>"},
12668 { 0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"},
12669 { 0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c>.w <Rd>, <Rm> {,<shift>}"},
12683 { 0xfffff800, 0x00001000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
12684 { 0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
12687 { 0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12689 { 0xfffff800, 0x00000000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},
12690 { 0xffef8030, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"},
12693 { 0xffe0f0f0, 0xfa00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
12695 { 0xfffff800, 0x00000800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"},
12696 { 0xffef8030, 0xea4f0010, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"},
12699 { 0xffe0f0f0, 0xfa20f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12701 { 0xffeff0f0, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"},
12703 { 0xffef8030, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"},
12706 { 0xffe0f0f0, 0xfa60f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
12710 { 0xfff0f0f0, 0xfb00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>" },
12785 { 0xfff00000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]" },
12797 { 0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>" },
12798 { 0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
12799 { 0xffffffc0, 0x0000b200, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>" },
12800 { 0xfffff080, 0xfa0ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}" },
12801 { 0xffffffc0, 0x0000b2c0, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>" },
12802 { 0xfffff080, 0xfa5ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
12803 { 0xffffffc0, 0x0000b280, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>" },
12804 { 0xfffff080, 0xfa1ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}" },
13330 // Write the result to the ARM core register Rd, and optionally update the
13351 const uint32_t Rd,
13356 if (Rd == 15)
13364 switch (Rd)
13376 reg_num = dwarf_r0 + Rd;
