Lines Matching refs:Rm
739 uint32_t Rm; // the source register
745 Rm = Bits32(opcode, 6, 3);
752 Rm = Bits32(opcode, 5, 3);
759 Rm = Bits32(opcode, 3, 0);
762 if (setflags && (BadReg(Rd) || BadReg(Rm)))
765 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
770 Rm = Bits32(opcode, 3, 0);
780 uint32_t result = ReadCoreReg(Rm, &success);
784 // The context specifies that Rm is to be moved into Rd.
788 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
956 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
969 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1124 uint32_t Rm; // the source register
1127 uint32_t shift_n; // the shift applied to the value read from Rm
1133 Rm = Bits32(opcode, 5, 3);
1142 Rm = Bits32(opcode, 3, 0);
1146 if (BadReg(Rd) || BadReg(Rm))
1151 Rm = Bits32(opcode, 3, 0);
1159 uint32_t value = ReadCoreReg(Rm, &success);
1390 uint32_t Rm; // the second operand
1393 Rm = Bits32(opcode, 6, 3);
1398 int32_t reg_value = ReadCoreReg(Rm, &success);
1410 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, other_reg);
1548 uint32_t Rm; // the register with the target address
1552 Rm = Bits32(opcode, 6, 3);
1554 if (Rm == 15)
1561 Rm = Bits32(opcode, 3, 0);
1563 if (Rm == 15)
1569 addr_t target = ReadCoreReg (Rm, &success);
1573 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1600 uint32_t Rm; // the register with the target address
1603 Rm = Bits32(opcode, 6, 3);
1608 Rm = Bits32(opcode, 3, 0);
1614 addr_t target = ReadCoreReg (Rm, &success);
1619 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1654 uint32_t Rm; // the register with the target address
1657 Rm = Bits32(opcode, 19, 16);
1658 if (BadReg(Rm))
1664 Rm = Bits32(opcode, 3, 0);
1665 if (Rm == 15)
1672 addr_t target = ReadCoreReg (Rm, &success);
1677 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
2392 uint32_t Rm; // the index register which contains an integer pointing to a byte/halfword in the table
2397 Rm = Bits32(opcode, 3, 0);
2399 if (Rn == 13 || BadReg(Rm))
2410 uint32_t base = ReadCoreReg(Rm, &success);
2415 uint32_t index = ReadCoreReg(Rm, &success);
2642 uint32_t Rd, Rn, Rm;
2644 uint32_t shift_n; // the shift applied to the value read from Rm
2651 Rm = Bits32(opcode, 8, 6);
2658 Rm = Bits32(opcode, 6, 3);
2662 if (Rn == 15 && Rm == 15)
2670 Rm = Bits32(opcode, 3, 0);
2684 uint32_t val2 = ReadCoreReg(Rm, &success);
2698 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, op2_reg);
2777 uint32_t Rm; // the second operand
2779 uint32_t shift_n; // the shift applied to the value read from Rm
2783 Rm = Bits32(opcode, 5, 3);
2789 Rm = Bits32(opcode, 3, 0);
2792 if (Rn == 15 || BadReg(Rm))
2797 Rm = Bits32(opcode, 3, 0);
2808 // Read the register value from register Rm.
2809 uint32_t val2 = ReadCoreReg(Rm, &success);
2901 uint32_t Rm; // the second operand
2903 uint32_t shift_n; // the shift applied to the value read from Rm
2907 Rm = Bits32(opcode, 5, 3);
2913 Rm = Bits32(opcode, 6, 3);
2916 if (Rn < 8 && Rm < 8)
2918 if (Rn == 15 || Rm == 15)
2923 Rm = Bits32(opcode, 3, 0);
2934 // Read the register value from register Rm.
2935 uint32_t val2 = ReadCoreReg(Rm, &success);
3190 uint32_t Rm; // the first operand register
3212 Rm = Bits32(opcode, 5, 3);
3223 Rm = Bits32(opcode, 3, 0);
3226 if (BadReg(Rd) || BadReg(Rm))
3231 Rm = Bits32(opcode, 3, 0);
3244 uint32_t value = ReadCoreReg (Rm, &success);
3280 uint32_t Rm; // the register whose bottom byte contains the amount to shift by
3287 Rm = Bits32(opcode, 5, 3);
3293 Rm = Bits32(opcode, 3, 0);
3295 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3301 Rm = Bits32(opcode, 11, 8);
3303 if (Rd == 15 || Rn == 15 || Rm == 15)
3314 // Get the Rm register content.
3315 uint32_t val = ReadCoreReg (Rm, &success);
4765 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4785 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4807 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5086 Rm);
5104 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5128 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5156 uint32_t Rm = ReadCoreReg (m, &success);
5165 uint32_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
5325 uint32_t Rd, Rn, Rm;
5327 uint32_t shift_n; // the shift applied to the value read from Rm
5333 Rm = Bits32(opcode, 5, 3);
5341 Rm = Bits32(opcode, 3, 0);
5344 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5350 Rm = Bits32(opcode, 3, 0);
5367 int32_t val2 = ReadCoreReg(Rm, &success);
5550 uint32_t Rd, Rn, Rm;
5552 uint32_t shift_n; // the shift applied to the value read from Rm
5559 Rm = Bits32(opcode, 5, 3);
5567 Rm = Bits32(opcode, 3, 0);
5573 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
5579 Rm = Bits32(opcode, 3, 0);
5596 uint32_t val2 = ReadCoreReg(Rm, &success);
5713 uint32_t Rd, Rn, Rm;
5715 uint32_t shift_n; // the shift applied to the value read from Rm
5722 Rm = Bits32(opcode, 5, 3);
5730 Rm = Bits32(opcode, 3, 0);
5733 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5739 Rm = Bits32(opcode, 3, 0);
5757 uint32_t val2 = ReadCoreReg(Rm, &success);
5958 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5976 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6003 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6033 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6045 addr_t offset = Shift (Rm, shift_t, shift_n, Bit32 (m_opcode_cpsr, APSR_C), &success);
6375 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6393 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6415 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6448 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6452 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
6794 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6813 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6834 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6864 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6868 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
7203 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7222 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7243 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7270 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7275 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
7630 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7649 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7671 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7699 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7708 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
7795 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7803 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7815 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7830 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7835 uint64_t rotated = ROR (Rm, rotation, &success);
7879 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7887 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7899 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7914 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7919 uint64_t rotated = ROR (Rm, rotation, &success);
7963 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7971 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7983 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7998 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8003 uint64_t rotated = ROR (Rm, rotation, &success);
8044 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8052 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8064 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8079 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8084 uint64_t rotated = ROR (Rm, rotation, &success);
8350 uint32_t Rd, Rn, Rm;
8352 uint32_t shift_n; // the shift applied to the value read from Rm
8359 Rm = Bits32(opcode, 5, 3);
8367 Rm = Bits32(opcode, 3, 0);
8373 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
8379 Rm = Bits32(opcode, 3, 0);
8397 uint32_t val2 = ReadCoreReg(Rm, &success);
8516 uint32_t Rd, Rn, Rm;
8518 uint32_t shift_n; // the shift applied to the value read from Rm
8525 Rm = Bits32(opcode, 5, 3);
8533 Rm = Bits32(opcode, 3, 0);
8539 if (BadReg(Rd) || Rn == 13 || BadReg(Rm))
8545 Rm = Bits32(opcode, 3, 0);
8562 uint32_t val2 = ReadCoreReg(Rm, &success);
8679 uint32_t Rm; // the second operand
8682 uint32_t shift_n; // the shift applied to the value read from Rm
8687 Rm = Bits32(opcode, 3, 0);
8691 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8697 Rm = Bits32(opcode, 3, 0);
8713 // Read the register value from register Rm.
8714 uint32_t val2 = ReadCoreReg(Rm, &success);
8818 uint32_t Rm; // the second operand
8821 uint32_t shift_n; // the shift applied to the value read from Rm
8826 Rm = Bits32(opcode, 3, 0);
8842 // Read the register value from register Rm.
8843 uint32_t val2 = ReadCoreReg(Rm, &success);
8955 uint32_t Rm; // the second operand
8958 uint32_t shift_n; // the shift applied to the value read from Rm
8962 Rm = Bits32(opcode, 5, 3);
8970 Rm = Bits32(opcode, 3, 0);
8973 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8979 Rm = Bits32(opcode, 3, 0);
8995 // Read the register value from register Rm.
8996 uint32_t val2 = ReadCoreReg(Rm, &success);
9249 uint32_t Rn, Rm;
9251 uint32_t shift_n; // the shift applied to the value read from Rm
9257 Rm = Bits32(opcode, 3, 0);
9259 if (BadReg(Rn) || BadReg(Rm))
9264 Rm = Bits32(opcode, 3, 0);
9277 uint32_t val2 = ReadCoreReg(Rm, &success);
9373 uint32_t Rn, Rm;
9375 uint32_t shift_n; // the shift applied to the value read from Rm
9381 Rm = Bits32(opcode, 5, 3);
9387 Rm = Bits32(opcode, 3, 0);
9389 if (BadReg(Rn) || BadReg(Rm))
9394 Rm = Bits32(opcode, 3, 0);
9407 uint32_t val2 = ReadCoreReg(Rm, &success);
9459 // d = UInt(Rd); m = UInt(Rm); setflags = (S == ?1?);
9477 // d = UInt(Rd); m = UInt(Rm); setflags = (S == ?1?);
9495 uint32_t Rm = ReadCoreReg (m, &success);
9499 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
9557 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
9584 uint32_t Rm = ReadCoreReg (m, &success);
9588 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
9657 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock();
9672 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ?1?);
9689 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ?1?);
9709 uint32_t Rm = ReadCoreReg (m, &success);
9713 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
10240 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10280 uint32_t Rm = ReadCoreReg (m, &success);
10289 offset_addr = Rn + Rm;
10291 offset_addr = Rn - Rm;
10515 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10561 uint32_t Rm = ReadCoreReg (m, &success);
10568 offset_addr = Rn + Rm;
10570 offset_addr = Rn - Rm;
11357 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11392 uint32_t Rm = ReadCoreReg (m, &success);
11398 offset = Rm;
11529 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11564 uint32_t Rm = ReadCoreReg (m, &success);
11570 offset = Rm;
11692 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11731 uint32_t Rm = ReadCoreReg (m, &success);
11737 offset = Rm;
11869 Rm);
11903 uint32_t Rm = ReadCoreReg (m, &success);
11909 offset = Rm;
11991 //d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
12029 uint32_t Rm = ReadCoreReg (m, &success);
12035 offset = Rm;
12136 // n = UInt(Rn); m = UInt(Rm); register_form = TRUE;
12154 uint32_t Rm = ReadCoreReg (m, &success);
12158 operand2 = Shift (Rm, shift_t, shift_n, APSR_C, &success);
12283 { 0x0fef0010, 0x004d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" },
12314 { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
12316 { 0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
12318 { 0x0ffffff0, 0x012fff20, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
12326 { 0x0fe00010, 0x00a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12330 { 0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDReg, "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12332 { 0x0fe00090, 0x00800010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRegShift, "add{s}<c> <Rd>, <Rn>, <Rm>, <type> <RS>"},
12339 { 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12343 { 0x0fe00010, 0x01c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12347 { 0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12351 { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12355 { 0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12359 { 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12363 { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12369 { 0x0fe00010, 0x00400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"},
12373 { 0x0ff0f010, 0x01300000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12377 { 0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rn>, <Rm> {,<shift>}"},
12383 { 0x0fef0ff0, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"},
12387 { 0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c> <Rd>, <Rm> {,<shift>}"},
12391 { 0x0ff0f010, 0x01700000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
12395 { 0x0ff0f010, 0x01500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm> {,<shift>}"},
12397 { 0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"},
12399 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
12401 { 0x0fef0070, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"},
12403 { 0x0fef00f0, 0x01a00010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
12405 { 0x0fef0070, 0x01a00020, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"},
12407 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
12409 { 0x0fef0ff0, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"},
12411 { 0x0fef0070, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"},
12413 { 0x0fef00f0, 0x01a00070, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
12415 { 0x0fe000f0, 0x00000090, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>" },
12419 { 0x0e10f010, 0x0010f000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,<Rn>,<Rm{,<shift>}" },
12429 { 0x0e500010, 0x06100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}" },
12431 { 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" },
12433 { 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12436 { 0x0e5000f0, 0x001000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12439 { 0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12441 { 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12446 { 0xffb00000, 0xf4200000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12447 { 0xffb00300, 0xf4a00000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Single, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12448 { 0xffb00f00, 0xf4a00c00, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12457 Rm> {<shift>}]{!}" },
12458 { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,+/-<Rm>[{!}" },
12463 { 0x0e500ff0, 0x000000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDReg, "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12468 { 0xffb00000, 0xf4000000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Multiple, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12469 { 0xffb00300, 0xf4800000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12474 { 0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}" },
12475 { 0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}" },
12476 { 0x0fff00f0, 0x06ef0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}" },
12477 { 0x0fff00f0, 0x06ff0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}" },
12520 { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPRm, "add sp, <Rm>"},
12524 { 0xffef8000, 0xebad0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" },
12570 { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
12572 { 0xffffff87, 0x00004700, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
12574 { 0xfff0ffff, 0xf3c08f00, ARMV5J_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
12578 { 0xfff0fff0, 0xe8d0f000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbb<c> <Rn>, <Rm>"},
12580 { 0xfff0fff0, 0xe8d0f010, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"},
12588 { 0xffffffc0, 0x00004140, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADCReg, "adcs|adc<c> <Rdn>, <Rm>"},
12589 { 0xffe08000, 0xeb400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12591 { 0xfffffe00, 0x00001800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
12592 // Make sure "add sp, <Rm>" comes before this instruction, so there's no ambiguity decoding the two.
12593 { 0xffffff00, 0x00004400, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDReg, "add<c> <Rdn>, <Rm>"},
12601 { 0xffffffc0, 0x00004000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateANDReg, "ands|and<c> <Rdn>, <Rm>"},
12602 { 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12606 { 0xffffffc0, 0x00004380, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateBICReg, "bics|bic<c> <Rdn>, <Rm>"},
12607 { 0xffe08000, 0xea200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12611 { 0xffffffc0, 0x00004040, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateEORReg, "eors|eor<c> <Rdn>, <Rm>"},
12612 { 0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12616 { 0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateORRReg, "orrs|orr<c> <Rdn>, <Rm>"},
12617 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12622 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12626 { 0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc<c> <Rdn>, <Rm>"},
12627 { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12642 { 0xfffffe00, 0x00001a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
12643 { 0xffe08000, 0xeba00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"},
12647 { 0xfff08f00, 0xea900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12651 { 0xffffffc0, 0x00004200, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rdn>, <Rm>"},
12652 { 0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c>.w <Rn>, <Rm> {,<shift>}"},
12656 { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"},
12658 { 0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"},
12659 // mov{s}<c>.w <Rd>, <Rm>
12660 { 0xffeff0f0, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"},
12668 { 0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"},
12669 { 0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c>.w <Rd>, <Rm> {,<shift>}"},
12673 { 0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm>"},
12674 { 0xfff08f00, 0xeb100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
12678 // cmp (register) (Rn and Rm both from r0-r7)
12679 { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
12680 // cmp (register) (Rn and Rm not both from r0-r7)
12681 { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
12683 { 0xfffff800, 0x00001000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
12684 { 0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
12686 { 0xffffffc0, 0x00004100, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRReg, "asrs|asr<c> <Rdn>, <Rm>"},
12687 { 0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12689 { 0xfffff800, 0x00000000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},
12690 { 0xffef8030, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"},
12692 { 0xffffffc0, 0x00004080, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSLReg, "lsls|lsl<c> <Rdn>, <Rm>"},
12693 { 0xffe0f0f0, 0xfa00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
12695 { 0xfffff800, 0x00000800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"},
12696 { 0xffef8030, 0xea4f0010, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"},
12698 { 0xffffffc0, 0x000040c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSRReg, "lsrs|lsr<c> <Rdn>, <Rm>"},
12699 { 0xffe0f0f0, 0xfa20f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12701 { 0xffeff0f0, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"},
12703 { 0xffef8030, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"},
12705 { 0xffffffc0, 0x000041c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateRORReg, "rors|ror<c> <Rdn>, <Rm>"},
12706 { 0xffe0f0f0, 0xfa60f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
12710 { 0xfff0f0f0, 0xfb00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>" },
12735 { 0xfffffe00, 0x00005800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]" },
12736 { 0xfff00fc0, 0xf8500000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c>.w <Rt>, [<Rn>,<Rm>{,LSL #<imm2>}]" },
12741 { 0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]" },
12742 { 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12747 { 0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>, [<Rn>,<Rm>]" },
12748 { 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12752 { 0xfffffe00, 0x00005600, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,<Rm>]" },
12753 { 0xfff00fc0, 0xf9100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12757 { 0xfffffe00, 0x00005e00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,<Rm>]" },
12758 { 0xfff00fc0, 0xf9300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12764 { 0xffb00000, 0xf9200000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
12765 { 0xffb00300, 0xf9a00000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Single, "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
12766 { 0xffb00f00, 0xf9a00c00, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12778 { 0xfffffe00, 0x00005000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]" },
12779 { 0xfff00fc0, 0xf8400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c>.w <Rt>, [<Rn>, <Rm> {lsl #imm2>}]" },
12783 { 0xfffffe00, 0x00005200, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]" },
12784 { 0xfff00fc0, 0xf8200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12791 { 0xffb00000, 0xf9000000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Multiple, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12792 { 0xffb00300, 0xf9800000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12797 { 0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>" },
12798 { 0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
12799 { 0xffffffc0, 0x0000b200, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>" },
12800 { 0xfffff080, 0xfa0ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}" },
12801 { 0xffffffc0, 0x0000b2c0, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>" },
12802 { 0xfffff080, 0xfa5ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
12803 { 0xffffffc0, 0x0000b280, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>" },
12804 { 0xfffff080, 0xfa1ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}" },
