Lines Matching refs:Or
42 /// large sizes or splitting up large values into small values) as well as
92 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// performs the same shuffe in terms of order or result bytes, but on a type
250 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
262 // fp stack or PPC FP unit).
443 // then bitconvert to floating point or vector.
566 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
589 // with a "move to register" or "extload into register" instruction, then
605 // Truncate or zero extend offset to target pointer type.
1027 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1057 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1121 // loads, whether they are legal or not, and then we end up here
1644 /// If the SETCC has been legalized using AND / OR, then the legalized node
1655 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1692 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1708 // or ordered version of the opcode.
1710 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1738 // If we aren't the ordered or unorder operation,
2479 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2480 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2501 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2503 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2509 //pseudo-op, or, even better, for whole-function isel.
2519 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2525 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2595 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2637 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2689 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2697 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2698 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2699 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2715 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2716 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2717 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2718 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2719 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2720 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2721 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2791 Op = DAG.getNode(ISD::OR, dl, VT, Op,
3189 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
3684 // See if multiply or divide can be lowered using two-result operations.
3714 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3721 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3873 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3915 // RelocBase can be JumpTable, GOT or some sort of global base.
3953 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
4013 // version (or vice versa).
4044 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
4205 && "VAARG promotion is supported only for vectors or integer types");
4224 case ISD::OR:
