Lines Matching refs:Or
67 /// some float libcalls (6, 8 or 12 bits).
100 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
163 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
194 // zero or sign-extension.
235 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
262 // If the register was not expanded, truncate or copy the value,
278 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
559 // If the register was not expanded, promote or copy the value,
575 /// RegsForValue - This struct represents the registers (physical or virtual)
578 /// time, but struct or array values are handled element-wise as multiple
581 /// necessarily have legal types, so each value may require one or more
586 /// may need be promoted or synthesized from one or more registers.
592 /// register or registers are. (Individual values are never synthesized
602 /// Each legal or promoted value requires one register, and each
670 // A Value with type {} or [0 x %t] needs no registers.
872 /// or PHI node updating; that information is cleared out as it is
896 /// a store or any other node that may need to be ordered after any
1117 "Unknown struct or array constant!");
1332 // If this is an argument, we can export it if the BB is the entry block or
1373 /// This function emits a branch and is used at the leaves of an OR or an
1436 // If this node is not part of the or/and tree, emit it as a branch.
1454 if (Opc == Instruction::Or) {
1526 /// If we should emit this as a bunch of and/or'd together conditions, return
1532 // If this is two comparisons of the same values or'd or and'd together, they
1572 // If this is not a fall-through branch or optimizations are switched off,
1587 // If this is a series of conditions that are or'd or and'd together, emit
1588 // this as a sequence of branches instead of setcc's with and/or operations.
1595 // or C, F
1607 BOp->getOpcode() == Instruction::Or)) {
1753 // This value may be smaller or larger than the target's pointer type, and
1754 // therefore require extension or truncating.
2114 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2117 Or, DAG.getConstant(BigValue, VT),
2277 // we will either branch to the default case for the switch, or the jump
2431 // tree a bit, by recognizing that if SV is greater than or equal to the
2727 // If the range has few cases (two or less) emit a series of specific
2996 // We can either truncate, zero extend, or no-op, accordingly.
3004 // We can either truncate, zero extend, or no-op, accordingly.
3015 // either a BITCAST or a no-op.
3068 // specified sequential range [L, L+Pos). or is undef.
3229 // We can't use either concat vectors or extract subvectors so fall back to
3380 // If the index is smaller or larger than intptr_t, truncate or extend
3430 // Handle alignment. If the requested alignment is less than or equal to
3431 // the stack alignment, ignore it. If the size is greater than or equal to
3508 // they are side-effect free or do not alias. The optimizer should really
3662 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3869 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
4742 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4820 "Variable in DbgValueInst should be either null or a DIVariable.");
4866 // Don't handle byval struct arguments or VLAs, for example.
5532 /// value is equal or not-equal to zero.
5670 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5734 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
6037 /// CallOperand - If this is the result output operand or a clobber
6042 /// AssignedRegs - If this is a register or register class operand, this
6103 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6120 // If this is a constraint for a single physreg, or a constraint for a
6128 // If this is a FP input in an integer register (or visa versa) insert a bit
6261 // If this is an input or an indirect output, process the call argument.
6307 // other is floating point, or their sizes are different, flag it as an
6353 // If the operand is a float, integer, or vector constant, spill to a
6389 // Second pass - Loop over all of the operands, assigning virtual or physregs
6423 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6462 // Memory output, or 'other' output (e.g. 'X' constraint).
6473 // Otherwise, this is a register or register class output.
6681 // contain multiple different value types. The preg or vreg allocated may
6773 /// convention or require stack pointer adjustment. Only a subset of the
6809 /// or patchpoint target node's operand list.
6818 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6998 // becomes now the last or second to last operand).
7204 // either the register MVT and the actual EVT are the same size or that
7388 // or one register.
