Lines Matching defs:DestVT
129 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
130 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
1027 MVT DestVT = DestEVT.getSimpleVT();
1028 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
1029 DestVT != MVT::f64)
1057 switch (DestVT.SimpleTy) {
1074 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1119 MVT DestVT;
1120 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1134 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
1136 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
1139 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
1141 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
1144 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
1152 MVT DestVT;
1153 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1155 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
1178 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
1180 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
1183 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
1185 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
1188 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1223 MVT DestVT = VA.getLocVT();
1225 Arg = EmitIntExt(SrcVT, Arg, DestVT, /*isZExt*/ false);
1233 MVT DestVT = VA.getLocVT();
1235 Arg = EmitIntExt(SrcVT, Arg, DestVT, /*isZExt*/ true);
1615 MVT DestVT = VA.getValVT();
1617 if (RVVT != DestVT) {
1625 SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
1658 MVT DestVT = DestEVT.getSimpleVT();
1663 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
1664 DestVT != MVT::i1)
1676 switch (DestVT.SimpleTy) {
1707 unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
1708 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
1709 DestVT == MVT::i64) &&
1712 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1713 DestVT = MVT::i32;
1723 if (DestVT == MVT::i64) {
1736 if (DestVT == MVT::i64) {
1750 unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1752 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
1755 // DestVT are odd things, so test to make sure that they are both types we can
1756 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1758 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
1759 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
1771 return Emiti1Ext(SrcReg, DestVT, isZExt);
1773 if (DestVT == MVT::i64)
1780 if (DestVT == MVT::i64)
1787 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
1794 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1795 DestVT = MVT::i32;
1796 else if (DestVT == MVT::i64) {
1806 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1836 MVT DestVT = DestEVT.getSimpleVT();
1837 unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
1849 MVT DestVT = DestEVT.getSimpleVT();
1850 if (DestVT != MVT::i64 && DestVT != MVT::i32)
1854 bool is64bit = (DestVT == MVT::i64);
1874 unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
1880 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
