Lines Matching refs:Lane
67 unsigned Reg, unsigned Lane,
73 unsigned DReg, unsigned Lane,
88 DebugLoc DL, unsigned DReg, unsigned Lane,
428 unsigned Reg, unsigned Lane, bool QPR) {
437 .addImm(Lane));
442 // Creates a SPR register from a DPR by copying the value in lane 0.
447 unsigned DReg, unsigned Lane,
454 .addReg(DReg, 0, Lane);
498 DebugLoc DL, unsigned DReg, unsigned Lane,
507 .addImm(Lane);
564 unsigned Lane;
566 case ARM::ssub_0: Lane = 0; break;
567 case ARM::ssub_1: Lane = 1; break;
568 default: llvm_unreachable("Unknown preferred lane!");
577 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
602 // lane, and the other lane(s) of the DPR/QPR register
