Lines Matching refs:Lane
67 bool HasLane; // True if instruction has an extra "lane" operand.
4004 unsigned SReg, unsigned &Lane) {
4006 Lane = 0;
4011 Lane = 1;
4018 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4026 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4027 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4028 /// lane of the DPR).
4035 unsigned DReg, unsigned Lane,
4037 // If the DPR is defined or used already, the other SPR lane will be chained
4046 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4064 unsigned Lane;
4103 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4105 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4106 // Note that DSrc has been widened and the other lane may be undef, which
4111 .addImm(Lane));
4126 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4129 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4135 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4141 .addImm(Lane);
4172 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4191 // the position based purely on the combination of lane-0 and lane-1
4199 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
