Lines Matching refs:MIB
691 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
692 MIB.addReg(SrcReg, getKillRegState(KillSrc));
694 MIB.addReg(SrcReg, getKillRegState(KillSrc));
695 AddDefaultPred(MIB);
784 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
788 return MIB.addReg(Reg, State);
791 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
792 return MIB.addReg(Reg, State, SubIdx);
832 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
833 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
834 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
835 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
837 AddDefaultPred(MIB);
841 MachineInstrBuilder MIB =
844 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
845 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
876 MachineInstrBuilder MIB =
880 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
881 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
882 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
897 MachineInstrBuilder MIB =
901 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
902 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
903 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
904 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
911 MachineInstrBuilder MIB =
915 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
916 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
917 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
918 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
919 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
920 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
921 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
922 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1020 MachineInstrBuilder MIB;
1023 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1024 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1025 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1026 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1028 AddDefaultPred(MIB);
1032 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1034 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1035 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1039 MIB.addReg(DestReg, RegState::ImplicitDefine);
1064 MachineInstrBuilder MIB =
1068 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1069 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1070 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1072 MIB.addReg(DestReg, RegState::ImplicitDefine);
1084 MachineInstrBuilder MIB =
1088 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1089 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1090 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1091 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1093 MIB.addReg(DestReg, RegState::ImplicitDefine);
1100 MachineInstrBuilder MIB =
1104 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1105 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1106 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1107 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1108 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1109 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1110 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1111 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1113 MIB.addReg(DestReg, RegState::ImplicitDefine);
1212 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1224 AddDefaultPred(MIB);
1231 MIB.addReg(SrcRegS, RegState::Implicit);
1308 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1311 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1989 MachineInstrBuilder MIB(MF, &*MI);
1991 MIB.addOperand(RegList[i]);
4065 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4087 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4109 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4115 MIB.addReg(SrcReg, RegState::Implicit);
4138 MIB.addReg(DReg, RegState::Define)
4142 AddDefaultPred(MIB);
4146 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4148 MIB.addReg(ImplicitSReg, RegState::Implicit);
4174 MIB.addReg(DDst, RegState::Define)
4177 AddDefaultPred(MIB);
4181 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4182 MIB.addReg(SrcReg, RegState::Implicit);
4184 MIB.addReg(ImplicitSReg, RegState::Implicit);
4222 MIB.addReg(DDst, RegState::Define);
4228 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4232 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4234 MIB.addImm(1);
4235 AddDefaultPred(MIB);
4238 MIB.addReg(SrcReg, RegState::Implicit);
4242 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4244 MIB.addReg(ImplicitSReg, RegState::Implicit);
