Lines Matching refs:MIB
389 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
406 MIB.addOperand(MI.getOperand(OpIdx++));
409 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
413 MIB.addOperand(MI.getOperand(OpIdx++));
423 MIB.addOperand(MI.getOperand(OpIdx++));
424 MIB.addOperand(MI.getOperand(OpIdx++));
431 MIB.addOperand(MO);
434 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
435 TransferImpOps(MI, MIB, MIB);
438 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
454 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
458 MIB.addOperand(MI.getOperand(OpIdx++));
461 MIB.addOperand(MI.getOperand(OpIdx++));
462 MIB.addOperand(MI.getOperand(OpIdx++));
465 MIB.addOperand(MI.getOperand(OpIdx++));
472 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
474 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
476 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
478 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
481 MIB.addOperand(MI.getOperand(OpIdx++));
482 MIB.addOperand(MI.getOperand(OpIdx++));
485 MIB->addRegisterKilled(SrcReg, TRI, true);
487 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
488 TransferImpOps(MI, MIB, MIB);
491 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
508 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
530 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
532 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
534 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
536 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
540 MIB.addOperand(MI.getOperand(OpIdx++));
543 MIB.addOperand(MI.getOperand(OpIdx++));
544 MIB.addOperand(MI.getOperand(OpIdx++));
547 MIB.addOperand(MI.getOperand(OpIdx++));
557 MIB.addReg(D0, SrcFlags);
559 MIB.addReg(D1, SrcFlags);
561 MIB.addReg(D2, SrcFlags);
563 MIB.addReg(D3, SrcFlags);
566 MIB.addImm(Lane);
570 MIB.addOperand(MI.getOperand(OpIdx++));
571 MIB.addOperand(MI.getOperand(OpIdx++));
575 MIB.addOperand(MO);
578 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
579 TransferImpOps(MI, MIB, MIB);
581 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
592 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
596 MIB.addOperand(MI.getOperand(OpIdx++));
598 MIB.addOperand(MI.getOperand(OpIdx++));
604 MIB.addReg(D0);
607 MIB.addOperand(MI.getOperand(OpIdx++));
610 MIB.addOperand(MI.getOperand(OpIdx++));
611 MIB.addOperand(MI.getOperand(OpIdx++));
614 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
615 TransferImpOps(MI, MIB, MIB);
918 MachineInstrBuilder MIB =
924 TransferImpOps(MI, MIB, MIB);
930 MachineInstrBuilder MIB;
932 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
937 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
941 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
942 TransferImpOps(MI, MIB, MIB);
999 MachineInstrBuilder MIB =
1003 MIB.addImm(0);
1004 AddDefaultPred(MIB);
1007 MachineInstrBuilder MIB =
1014 AddDefaultPred(MIB);
1070 MachineInstrBuilder MIB =
1077 TransferImpOps(MI, MIB, MIB);
1083 MachineInstrBuilder MIB =
1092 MIB.addOperand(MI.getOperand(OpIdx++));
1095 MIB.addOperand(MI.getOperand(OpIdx++));
1096 MIB.addOperand(MI.getOperand(OpIdx++));
1101 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1105 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1106 TransferImpOps(MI, MIB, MIB);
1107 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1114 MachineInstrBuilder MIB =
1123 MIB.addOperand(MI.getOperand(OpIdx++));
1126 MIB.addOperand(MI.getOperand(OpIdx++));
1127 MIB.addOperand(MI.getOperand(OpIdx++));
1132 MIB.addReg(D0).addReg(D1);
1135 MIB->addRegisterKilled(SrcReg, TRI, true);
1137 TransferImpOps(MI, MIB, MIB);
1138 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
