Lines Matching refs:BUILD_VECTOR
115 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
559 setTargetDAGCombine(ISD::BUILD_VECTOR);
1039 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
4984 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5045 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5071 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5081 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5388 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5391 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5437 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5440 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5544 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5605 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5610 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5615 BVN->getOpcode() != ISD::BUILD_VECTOR)
5636 if (N->getOpcode() != ISD::BUILD_VECTOR)
5660 /// or a constant BUILD_VECTOR with sign-extended elements.
5670 /// or a constant BUILD_VECTOR with zero-extended elements.
5741 /// extending load, or BUILD_VECTOR with extended elements, return the
5756 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5760 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5761 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5763 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5766 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5767 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5780 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
5901 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5937 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6046 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6234 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
7700 || N0.getOpcode() != ISD::BUILD_VECTOR
7701 || N1.getOpcode() != ISD::BUILD_VECTOR)
7710 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
8602 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8617 /// ISD::BUILD_VECTOR.
8620 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8646 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8650 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8653 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8656 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8683 // i32, turn the build_vector into a sequence of insert_vector_elt.
8714 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
9115 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9166 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9194 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9196 /// build_vector must have the same constant integer value.
9213 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9225 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9637 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
9657 case ARMISD::BUILD_VECTOR:
