Lines Matching refs:VA
1267 CCValAssign VA = RVLocs[i];
1272 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1279 if (VA.needsCustom()) {
1281 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1285 VA = RVLocs[++i]; // skip ahead to next loc
1286 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1294 if (VA.getLocVT() == MVT::v2f64) {
1299 VA = RVLocs[++i]; // skip ahead to next loc
1300 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1303 VA = RVLocs[++i]; // skip ahead to next loc
1304 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1314 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1320 switch (VA.getLocInfo()) {
1324 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1339 const CCValAssign &VA,
1341 unsigned LocMemOffset = VA.getLocMemOffset();
1352 CCValAssign &VA, CCValAssign &NextVA,
1360 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1449 CCValAssign &VA = ArgLocs[i];
1455 switch (VA.getLocInfo()) {
1459 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1462 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1465 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1468 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1473 if (VA.needsCustom()) {
1474 if (VA.getLocVT() == MVT::v2f64) {
1481 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1483 VA = ArgLocs[++i]; // skip ahead to next loc
1484 if (VA.isRegLoc()) {
1486 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1488 assert(VA.isMemLoc());
1491 dl, DAG, VA
1494 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1497 } else if (VA.isRegLoc()) {
1499 assert(VA.getLocVT() == MVT::i32 &&
1505 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1507 assert(VA.isMemLoc());
1541 unsigned LocMemOffset = VA.getLocMemOffset();
1557 assert(VA.isMemLoc());
1560 dl, DAG, VA, Flags));
2002 CCValAssign &VA = ArgLocs[i];
2003 EVT RegVT = VA.getLocVT();
2006 if (VA.getLocInfo() == CCValAssign::Indirect)
2008 if (VA.needsCustom()) {
2013 if (!VA.isRegLoc())
2023 } else if (!VA.isRegLoc()) {
2024 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2105 CCValAssign &VA = RVLocs[i];
2106 assert(VA.isRegLoc() && "Can only return in registers!");
2110 switch (VA.getLocInfo()) {
2114 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2118 if (VA.needsCustom()) {
2119 if (VA.getLocVT() == MVT::v2f64) {
2126 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2130 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2131 VA = RVLocs[++i]; // skip ahead to next loc
2132 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2136 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2137 VA = RVLocs[++i]; // skip ahead to next loc
2147 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2151 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2152 VA = RVLocs[++i]; // skip ahead to next loc
2153 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2157 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2162 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2687 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2700 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2946 CCValAssign &VA = ArgLocs[i];
2947 if (VA.isMemLoc()) {
2948 int index = VA.getValNo();
2982 CCValAssign &VA = ArgLocs[i];
2983 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2984 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2986 if (VA.isRegLoc()) {
2987 EVT RegVT = VA.getLocVT();
2989 if (VA.needsCustom()) {
2992 if (VA.getLocVT() == MVT::v2f64) {
2993 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2995 VA = ArgLocs[++i]; // skip ahead to next loc
2997 if (VA.isMemLoc()) {
2998 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3004 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3013 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3032 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3039 switch (VA.getLocInfo()) {
3043 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3047 DAG.getValueType(VA.getValVT()));
3048 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3052 DAG.getValueType(VA.getValVT()));
3053 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3059 } else { // VA.isRegLoc()
3062 assert(VA.isMemLoc());
3063 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3084 Ins[VA.getValNo()].PartOffset,
3085 VA.getLocMemOffset(),
3095 unsigned FIOffset = VA.getLocMemOffset();
3096 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3101 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
