Lines Matching full:b0000
887 let Inst{7-4} = 0b0000;
1084 let Inst{26-23} = 0b0000;
1104 let Inst{26-23} = 0b0000;
1866 let Inst{7-4} = 0b0000;
2142 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2143 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2144 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2145 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2146 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2147 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2194 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2200 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2340 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2531 let Inst{7-4} = 0b0000; // Multiply
2542 let Inst{7-4} = 0b0000; // Multiply
2559 def t2SMULL : T2MulLong<0b000, 0b0000,
2564 def t2UMULL : T2MulLong<0b010, 0b0000,
2571 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2577 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2601 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2622 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2643 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2841 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2853 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2865 0, 0b010, 0b0000, (outs rGPR:$Rd),
2874 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
3131 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3963 let Inst{7-0} = 0b0000;
3973 let Inst{7-0} = 0b0000;
