Lines Matching refs:MIB
515 MachineInstrBuilder MIB;
522 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
525 MIB.addReg(Base, getDefRegState(true))
535 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
536 MIB.addReg(Base, getKillRegState(BaseKill));
539 MIB.addImm(Pred).addReg(PredReg);
542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
547 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
1053 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
1060 MIB.addOperand(MI->getOperand(OpNum));
1063 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1368 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1372 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1374 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1378 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2056 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
2064 MIB.addReg(0);
2065 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2066 concatenateMemOperands(MIB, Op0, Op1);
2067 DEBUG(dbgs() << "Formed " << *MIB << "\n");
2070 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
2078 MIB.addReg(0);
2079 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2080 concatenateMemOperands(MIB, Op0, Op1);
2081 DEBUG(dbgs() << "Formed " << *MIB << "\n");
