Lines Matching refs:Rm
1138 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1175 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1475 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1537 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1579 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1624 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1657 if (type && Rm == 15)
1671 if (!type && Rm == 15)
1684 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1701 if (!type && Rm == 15)
1719 if (!type && (Rt == 15 || Rm == 15))
1796 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1843 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2098 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2222 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2244 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2457 // The fixed offset encodes as Rm == 0xd, so we check for that.
2458 if (Rm == 0xd) {
2487 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2488 // variant encodes Rm == 0xf. Anything else is a register offset post-
2490 if (Rm != 0xD && Rm != 0xF &&
2491 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2569 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2623 if (Rm == 0xF)
2653 if (Rm == 0xD)
2655 else if (Rm != 0xF) {
2656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2838 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2859 if (Rm != 0xF) {
2868 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2869 // variant encodes Rm == 0xf. Anything else is a register offset post-
2871 if (Rm != 0xD && Rm != 0xF &&
2872 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2885 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2911 if (Rm != 0xF)
2918 if (Rm != 0xD && Rm != 0xF) {
2919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2933 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2942 if (Rm != 0xF) {
2951 if (Rm == 0xD)
2953 else if (Rm != 0xF) {
2954 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2968 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2996 if (Rm != 0xF) {
3005 if (Rm == 0xD)
3007 else if (Rm != 0xF) {
3008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3067 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3068 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3073 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3112 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3113 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3134 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3193 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3197 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3240 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3256 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3762 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3787 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3790 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3841 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3846 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4063 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4066 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4136 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4176 if (Rm != 0xF) { // Writeback
4183 if (Rm != 0xF) {
4184 if (Rm != 0xD) {
4185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4203 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4241 if (Rm != 0xF) { // Writeback
4248 if (Rm != 0xF) {
4249 if (Rm != 0xD) {
4250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4269 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4307 if (Rm != 0xF) { // Writeback
4314 if (Rm != 0xF) {
4315 if (Rm != 0xD) {
4316 Rm, Address, Decoder)))
4336 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4370 if (Rm != 0xF) { // Writeback
4377 if (Rm != 0xF) {
4378 if (Rm != 0xD) {
4379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4400 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4439 if (Rm != 0xF) { // Writeback
4446 if (Rm != 0xF) {
4447 if (Rm != 0xD) {
4448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4470 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4502 if (Rm != 0xF) { // Writeback
4509 if (Rm != 0xF) {
4510 if (Rm != 0xD) {
4511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4534 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4582 if (Rm != 0xF) { // Writeback
4589 if (Rm != 0xF) {
4590 if (Rm != 0xD) {
4591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4615 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4654 if (Rm != 0xF) { // Writeback
4661 if (Rm != 0xF) {
4662 if (Rm != 0xD) {
4663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4687 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4689 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4691 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4694 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4696 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4713 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4715 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4717 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4724 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4726 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4944 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4945 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4957 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
