Lines Matching defs:Encoded
267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
272 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
284 // In instruction code this value always encoded as lowest 12 bits,
307 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
312 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
313 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
314 return Encoded;
330 /// getSORegOpValue - Return an encoded so_reg shifted register value.
434 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
454 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
468 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
482 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
494 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
516 // Q registers are encoded as 2x their register number.
555 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
902 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
915 // FIXME: The immediate operand should have already been encoded like this
927 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
935 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
968 // FIXME: The immediate operand should have already been encoded like this
975 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1067 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1268 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1378 // Encoded as [Rn, Rm, imm].
1652 // Pseudo instructions don't get encoded.
