Lines Matching refs:MIB
128 MachineInstrBuilder MIB =
131 MIB = AddDefaultT1CC(MIB);
133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
136 AddDefaultPred(MIB);
240 const MachineInstrBuilder MIB =
243 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
259 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
261 MIB = AddDefaultT1CC(MIB);
262 MIB.addReg(DestReg).addImm(ThisVal);
263 MIB = AddDefaultPred(MIB);
264 MIB.setMIFlags(MIFlags);
267 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
269 MIB = AddDefaultT1CC(MIB);
270 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
271 MIB = AddDefaultPred(MIB);
272 MIB.setMIFlags(MIFlags);
350 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
388 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
416 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
565 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
676 AddDefaultPred(MIB);
