Lines Matching full:mips
1 //===-- MipsastISel.cpp - Mips FastISel implementation
163 ResultReg = createResultReg(&Mips::GPR32RegClass);
164 Opc = Mips::LW;
168 ResultReg = createResultReg(&Mips::GPR32RegClass);
169 Opc = Mips::LHu;
173 ResultReg = createResultReg(&Mips::GPR32RegClass);
174 Opc = Mips::LBu;
178 ResultReg = createResultReg(&Mips::FGR32RegClass);
179 Opc = Mips::LWC1;
183 ResultReg = createResultReg(&Mips::AFGR64RegClass);
184 Opc = Mips::LDC1;
222 Opc = Mips::SB;
225 Opc = Mips::SH;
228 Opc = Mips::SW;
231 Opc = Mips::SWC1;
234 Opc = Mips::SDC1;
301 EmitInst(Mips::RetRA);
325 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
327 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
328 EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
331 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
333 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
335 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
336 EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
346 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
353 EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
360 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
375 unsigned Opc = Mips::ADDiu;
376 EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
379 EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
387 EmitInst(Mips::LUi, TmpReg).addImm(Hi);
388 EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
390 EmitInst(Mips::LUi, ResultReg).addImm(Hi);
396 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
